Blocking and non-blocking assignments

In Verilog, blocking (=) and non-blocking (<=) assignments are fundamental concepts that play a critical role in defining the behavior of your code. Misunderstanding these assignments can lead to unexpected simulation results, making it vital for designers to grasp their differences and proper usage.

This article dives into the key distinctions between the two assignment types and provides examples to clarify their applications.

What are Blocking Assignments?

Blocking assignments, represented by the = operator, execute sequentially. Each assignment must complete before the next one begins. This sequential behavior resembles traditional programming languages and is ideal for modeling combinational logic in Verilog.

Syntax:

variable = expression;

Key Characteristics:

  • Executes statements in the order they are written.
  • Blocks subsequent statements until the current assignment is complete.
  • Typically used inside procedural blocks such as always or initial.

Example:

module blocking_example;
    reg a, b, c;

    initial begin
        a = 1;  // Statement 1
        b = a;  // Statement 2 depends on Statement 1
        c = b;  // Statement 3 depends on Statement 2
      
      //displaying values of a,b and c
      $display("value of a = %0d",a);
      $display("value of b = %0d",b);
      $display("value of c = %0d",c);
    end
endmodule

In the example above:

  1. a is assigned 1.
  2. The value of a is assigned to b.
  3. Finally, b is assigned to c.

Because of the blocking behavior, the execution order is straightforward and predictable.

Output:

value of a = 1
value of b = 1
value of c = 1

What are Non-Blocking Assignments?

Non-blocking assignments, represented by the <= operator, allow parallel execution. The right-hand side (RHS) of the assignment is evaluated immediately, but the actual assignment to the left-hand side (LHS) occurs later, at the end of the time step.

Syntax:

variable <= expression;

Key Characteristics:

  • Enables concurrent execution of statements.
  • The LHS value is updated after all RHS evaluations in the current time step.
  • Commonly used in sequential logic (e.g., flip-flops, registers).

Example:

module nonblocking_example;
    reg a, b, c;

    initial begin
        a <= 1;  // Statement 1
        b <= a;  // Statement 2, RHS evaluated before Statement 1 updates
        c <= b;  // Statement 3, RHS evaluated before Statement 2 updates
       #5;
      //displaying values of a,b and c
      $display("value of a = %0d",a);
      $display("value of b = %0d",b);
      $display("value of c = %0d",c);
    end
endmodule

In this case:

  • When a <= 1 executes, the RHS (1) is evaluated immediately, but a is updated at the end of the time step.
  • Similarly, b <= a captures the old value of a before it is updated.
  • c <= b captures the old value of b.

Since all the statements will be executed parallelly, a will get assigned as ‘1’ where b and c will be get assigned as ‘x’ as it is default value of reg. I am using #5 delay because display statement is executed in active region while non-blocking assignment will be executed in NBA region. You can read more about simulation regions in

https://vlsiworlds.com/scheduling-regions-in-system-verilog/

This behavior allows all assignments to occur simultaneously, mimicking the parallel behavior of hardware.

Output:

value of a = 1
value of b = x
value of c = x

Common Pitfalls and Best Practices

1. Mixing Blocking and Non-Blocking Assignments

Avoid mixing both types of assignments within the same procedural block to prevent simulation mismatches. Consider the following incorrect code:

always @(posedge clk) begin
    a = b;       // Blocking assignment
    b <= a + 1;  // Non-blocking assignment
end

Here, the behavior can become unpredictable because a = b executes immediately, while b <= a + 1 updates at the end of the time step.

Solution:

Stick to one type of assignment per procedural block:

always @(posedge clk) begin
    a <= b;
    b <= a + 1;
end

2. Using Blocking Assignments in Sequential Logic

Blocking assignments should not be used for sequential logic as they do not reflect the concurrent nature of hardware. For flip-flops and registers, always use non-blocking assignments.

3. Debugging Timing Issues

When debugging, be mindful of how values are updated across time steps. Misinterpreting the behavior of blocking and non-blocking assignments can lead to incorrect expectations.

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