Repeat and Forever Loop

SystemVerilog provides a variety of looping constructs to handle repetitive operations, including the repeat and forever loops. While these loops are primarily used in simulation and testbench design, they can also simplify hardware modeling. Additionally, the forever loop and the always block are often compared due to their infinite execution, but they serve distinct purposes.

The repeat Loop

The repeat loop executes a block of code a fixed number of times. It is particularly useful when the number of iterations is predetermined.

Syntax

repeat (n) begin
    // Code to be executed n times
end

n: Specifies the number of iterations. The loop terminates automatically after n iterations.

Example 1: Basic Usage of repeat

module repeat_example;
    initial begin
        int count = 0;

        // Repeat the loop 5 times
        repeat (5) begin
            count++;
            $display("Count = %0d", count);
        end
    end
endmodule

Output:

Count = 1
Count = 2
Count = 3
Count = 4
Count = 5

Example 2: Delayed Execution with repeat

module repeat_with_delay;
    initial begin
        int count = 0;

        // Repeat the loop 4 times with a delay of 10 time units
        repeat (4) begin
            #10;
            count++;
            $display("Time: %0t, Count = %0d", $time, count);
        end
    end
endmodule

The #10 introduces a delay of 10 time units between each iteration.

Output:

Time: 10, Count = 1
Time: 20, Count = 2
Time: 30, Count = 3
Time: 40, Count = 4

The forever Loop

The forever loop runs indefinitely, making it suitable for operations that require continuous execution. Unlike repeat, it does not have a termination condition.

Syntax

forever begin
    // Code to be executed continuously
end

Example 3: Basic Usage of forever

module forever_example;
    logic clk;

    initial begin
        clk = 0;

        // Toggle clock signal forever
        forever #5 clk = ~clk;  // Invert clk every 5 time units
        #50 $finish;
    end
endmodule

Explanation:

• The forever loop toggles the clock (clk) signal every 5 time units.
• The simulation will stop at time 50 otherwise it will run infinitely or an external condition terminates the loop.

Example 4: Conditional Termination in forever

module forever_with_condition;
    logic clk;
    int counter;

    initial begin
        clk = 0;
        counter = 0;

        // Generate a clock and terminate after 10 cycles
        forever begin
            #5 clk = ~clk;
              $display("counter = %0d",counter);
              counter++;
               if (counter == 10)
              break;
        end
      $display("Terminating at time: %0t", $time);
    end
endmodule

The forever loop is terminated conditionally after 10 iterations by using break statement.

Output:

counter = 0
counter = 1
counter = 2
counter = 3
counter = 4
counter = 5
counter = 6
counter = 7
counter = 8
counter = 9
Terminating at time: 50

Differences Between forever Loop and always Block

The forever loop and always block both execute infinitely but differ in their purpose and use cases.

Feature	forever Loop	always Block
Purpose	Used for repetitive simulation tasks.	Defines combinational or sequential logic in hardware.
Scope	Restricted to a procedural block (initial or always).	A continuous block that synthesizes into hardware. Can’t be use inside another procedural block.
Termination	Can be terminated conditionally or explicitly.	Cannot be terminated; always active during simulation.
Execution	Runs procedural code.	Models continuous or clock-driven behavior.
Use Case	Can be used inside a class. Generating clocks, periodic simulation tasks.	Can’t use inside class. Ideal for Flip-flops, latches, and combinational logic.

Example 5: forever vs. always

module forever_vs_always;
    logic clk1, clk2;

    // Using forever loop
    initial begin
        clk1 = 0;
        forever #10 clk1 = ~clk1;  // Generate clk1
    end

    // Using always block
    always begin
        #10 clk2 = ~clk2;  // Generate clk2
    end
endmodule

Explanation:

• The forever loop generates the clk1 signal within an initial block.
• The always block generates the clk2 signal and can’t be placed within an initial block.