UVM Sequence Item

A uvm_sequence_item is a SystemVerilog class that represents a transaction. It is used to communicate between the sequencer and the driver in a UVM testbench. It typically contains:

  • Data fields (representing a transaction)
  • Factory registration (for object creation and overrides)
  • Constructor
  • Constraints (to control randomized values)

To create a sequence item, we need to extend uvm_sequence_item and define the required fields.

Key Points:

  • The rand keyword allows automatic randomization of the fields when randomize() is called.
  • UVM allows adding constraints to limit the values generated during randomization.
  • To allow factory overrides and easy creation, we register the sequence item using `uvm_object_utils().

Example: Creating a basic transaction class

class my_transaction extends uvm_sequence_item;
    
    `uvm_object_utils(my_transaction)  // Register with UVM factory

    rand bit [7:0] addr;
    rand bit [31:0] data;
    rand bit write_enable;

    constraint addr_alignment { addr % 4 == 0; }
    constraint valid_data { if (write_enable) data != 0; }

    function new(string name = "my_transaction");
        super.new(name);
    endfunction

endclass
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