UVM RAL Predictor

A UVM RAL Predictor is responsible for updating the UVM register model with the expected values based on bus transactions. When a register write occurs, the predictor updates the register model to reflect the new value. When a read occurs, the predictor compares the expected value with the actual value read from the DUT.

Why is UVM RAL Predictor Important?

  • Keeps the UVM register model updated with the latest values.
  • Helps detect mismatches between expected and actual DUT register values.
  • Reduces the need for manual register value tracking.
  • Provides better debugging and coverage analysis.

There are two types of prediction methods in UVM:

1. Implicit Prediction

In implicit prediction, the UVM register model automatically updates itself without needing a predictor component. When a register write transaction occurs, the register model assumes that the written value has been successfully updated in the DUT.

Key Characteristics:
  • No need for a separate predictor – the register model updates itself automatically.
  • Works well for simple bus protocols with no response delay.
  • Assumes that all write operations succeed without verification.
  • Not suitable when the DUT modifies register values autonomously.
How to Enable Implicit Prediction?

Implicit prediction is enabled by default. However, you must explicitly configure it in the register model.

Enabling Implicit Prediction
// Enable implicit prediction for the register model
reg_model.default_map.set_auto_predict(1);

With this, whenever a register write operation occurs, the register model automatically updates its internal value without needing an external predictor.

Example: Register Write in Implicit Prediction

uvm_status_e status;

// Write a value to the register
reg_model.my_reg.write(status, 32'hA5A5A5A5, .parent(this));

// Read back the value (this reads from the register model, not DUT)
bit [31:0] read_data;
reg_model.my_reg.get(read_data);

`uvm_info("IMPLICIT_PRED", $sformatf("Predicted Value: 0x%0X", read_data), UVM_MEDIUM)

Key Observation:

  • The value read using get() is not read from the DUT.
  • The register model assumes the write was successful and updates itself.
  • If the DUT changes the register internally, the model won’t reflect it unless explicitly read from the DUT.

When to Use Implicit Prediction?

  • When the DUT does not modify registers autonomously.
  • When the verification team wants a simpler setup without a predictor.
  • For memory-mapped registers that do not change their values unexpectedly.

2. Explicit Prediction

In explicit prediction, the register model does not automatically update itself. Instead, a UVM Register Predictor listens to bus transactions and explicitly updates the register model based on the responses received from the DUT.

Key Characteristics:
  • Requires a UVM Register Predictor component.
  • Works well with complex DUTs where registers may be modified autonomously.
  • Ensures that the register model reflects actual DUT values.
  • Useful when register values change due to internal logic in the DUT.
How to Enable Explicit Prediction?

To enable explicit prediction, we must:

  1. Disable implicit prediction using set_auto_predict(0).
  2. Connect the predictor to the register model using set_predictor().
Setting Up Explicit Prediction
// Connect the register predictor to the register model
reg_model.default_map.set_predictor(reg_predictor);
Example: Implementing UVM RAL Predictor (Explicit Prediction)

Let’s create a UVM register predictor that updates the register model.

class my_reg_predictor extends uvm_reg_predictor#(apb_transfer);

  `uvm_component_utils(my_reg_predictor)

  function new(string name = "my_reg_predictor", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  virtual function void write(apb_transfer t);
    uvm_reg_bus_op rw;

    rw.kind = t.write ? UVM_WRITE : UVM_READ;
    rw.addr = t.addr;
    rw.data = t.data;
    rw.status = UVM_IS_OK;

    // Predict the new register value
    predict(rw);
  endfunction

endclass

Now, we integrate the predictor, adapter, and register model inside the UVM environment.

class my_env extends uvm_env;

  `uvm_component_utils(my_env)

  my_reg_block reg_model;
  apb_reg_adapter apb_adapter;
  my_reg_predictor reg_predictor;
  apb_sequencer apb_seqr;

  function new(string name = "my_env", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    reg_model = my_reg_block::type_id::create("reg_model", this);
    apb_adapter = apb_reg_adapter::type_id::create("apb_adapter", this);
    reg_predictor = my_reg_predictor::type_id::create("reg_predictor", this);
    apb_seqr = apb_sequencer::type_id::create("apb_seqr", this);

    reg_model.default_map.set_sequencer(apb_seqr, apb_adapter);

    // Connect the predictor to the register model
    reg_model.default_map.set_predictor(reg_predictor);
  endfunction

endclass

Writing a Test to Verify Register Read/Write Operations:

class reg_test_seq extends uvm_sequence#(apb_transfer);

  `uvm_object_utils(reg_test_seq)

  function new(string name = "reg_test_seq");
    super.new(name);
  endfunction

  virtual task body();
    uvm_status_e status;
    bit [31:0] read_data;

    `uvm_info("REG_TEST_SEQ", "Starting Register Test", UVM_MEDIUM)

    // Write to register
    reg_model.my_reg.write(status, 32'hDEADBEEF, .parent(this));

    // Read from register
    reg_model.my_reg.read(status, read_data, .parent(this));

    `uvm_info("REG_TEST_SEQ", $sformatf("Read Data: 0x%0X", read_data), UVM_MEDIUM)
  endtask

endclass

Key Observation:

  • The write() method does not automatically update the register model.
  • The predictor listens to bus transactions and explicitly updates the register model based on the bus response.
  • This ensures that only actual DUT responses update the register model.

When to Use Explicit Prediction?

  • When registers are modified by the DUT autonomously (e.g., status registers).
  • When using protocols with response delays (e.g., AXI, AHB, SPI).
  • When verification accuracy is critical and we cannot assume writes are always successful.

The UVM RAL Predictor ensures that the UVM register model accurately reflects register values in the DUT.

  • Implicit Prediction is simpler and assumes writes always succeed, but it fails if the DUT modifies registers independently.
  • Explicit Prediction is more accurate, requiring a UVM Register Predictor to track real DUT responses.
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