This article is contributed by my friend. He is currently working in Xilinx as a Digital Design Engineer.
The selection of candidates for interview was entirely based on resume. The interview consists of 3 rounds.
Round 1 (Technical):
The first round was entirely based on my resume. First they asked me to introduce yourself. After that the interview started. The interviewer asked me to explain all the MTech projects, that I have done and MTech Thesis. He also asked some cross questions regarding the projects. My suggestion for all the readers is Please read your resume thoroughly. This is the most important thing to crack any VLSI interview. If a simple word ‘synchronous’ is also written in your resume, prepare for it.
Round 2 and 3 :
- Calculation of FIFO depth.
- What is cross domain crossing?
- What is the difference between FF and Latch? Write the verilog code for both.
- Explain Static Timing Analysis.
- Calculate min frequency.
- Difference between STA and DTA.
- How to avoid latches in your design?
- What is the difference between synchronous and asynchronous reset along with verilog code.
- Some verilog basic questions
- Intra delay and inter delay.
- Verilog construct which is not supported by synthesis tool.
- Difference between ~ and ! (NOT Operation).
- Some more questions which I don’t remember now.
- VLSI Design flow.
- Some basic RTL code specific to my project.
- Some basic questions on memory (SRAM, DRAM and PLDs).
- What is FPGA?
- Function of CLB (and he also asked about slices)
- Some question related to Look Up Table (Like how it serially loaded to SRAM cells)
- Some specification of Xilinx FPGA you worked on.
- Which are the common file you need for synthesis a RTL design.
- Difference between .lib and .lef files ?
- System Verilog
- Difference between Function and Task
- Difference between Queue and Mailbox.
- Some question on Program Blocks
- Semaphore
- (some more questions which I don’t remember now).