The Universal Verification Methodology (UVM) is a widely adopted framework in the world of functional verification for designing reusable and scalable testbenches. Developed to address the challenges of verifying complex System-on-Chip (SOC) designs, UVM standardizes verification methodologies, making it easier for teams to collaborate, reuse components, and enhance verification efficiency. It is a library of classes and utilities built on System Verilog. It provides a structured approach to verification by defining reusable components, facilitating consistent practices across projects and teams. This tutorial will explore the components, architecture, and benefits of UVM, making it an indispensable tool for modern VLSI verification.
- UVM Testbench and Class Hierarchy
- UVM Object and Utility Macros
- UVM Sequence Item
- UVM Sequence Item Methods
- UVM Sequence
- Start a sequence
- UVM Sequence Macros
- UVM Phases
- UVM Sequencer
- m_sequencer and p_sequencer
- Virtual sequencer and virtual sequences
- uvm_config_db/uvm_resource_db in UVM
- UVM Driver
- UVM Monitor
- UVM Agent
- UVM Scoreboard
- UVM Subscriber
- UVM Environment
- UVM Test
- UVM testbench top
- UVM RAL Tutorial
- UVM TLM Tutorial
- UVM Callback
- UVM Callback in UVM Sequence