System Verilog Interview Questions

  • What is abstract class and pure virtual functions?
  • What is Associative array? How it is different from Dynamic array?
  • What are the types of assertions? What is difference between them?
  • What is polymorphism? Explain with help of an example.
  • What are the types of coverage? What are bins?
  • What is difference between ignore and illegal bins?
  • What is difference between struct and union?
  • How can we improve Functional coverage in SOC?
  • What is race condition? What is difference between program and module?
  • Difference between task and functions.
  • Why we use virtual interface?
  • What is clocking block and modport? Difference between them.
  • How can we override constraints?
  • Define Formal Verification and why it is used? At what stage will it come?
  • Difference between shallow copy and deep copy.
  • What is local and protected keyword?
  • Difference between blocking and non-blocking assignment?
  • Difference between $display, $monitor, $strobe and $write.
  • What are System Verilog regions?
  • Super Keyword in System Verilog.
  • Difference between AXI3 and AXI4 protocol.
  • Difference between AHB and AXI protocol.

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