case statement

A case statement in SystemVerilog is a multi-way branch statement used to select one out of several blocks of code based on the value of an expression. It is analogous to the switch-case construct in programming languages like C or Java. Case statements provide a clean, readable way to represent multiple conditional operations.

Syntax of a Case Statement

The basic syntax of a case statement in System Verilog is as follows:

case (expression)
  value1: begin
    // Statements for value1
  end
  value2: begin
    // Statements for value2
  end
  default: begin
    // Default statements
  end
endcase
  • expression: The variable or expression being tested.
  • value1, value2: Constant expressions that the main expression is compared against.
  • default: A catch-all block executed if none of the cases match. This is optional but recommended.

Types of Case Statements in SystemVerilog

  1. Standard Case This is the basic case statement where the expression is matched against a list of case items.
  2. Casez The casez statement allows the use of z (high-impedance) and ? (wildcard) in the case items as don’t care condition.
  3. Casex The casex statement treats both x (unknown) and z in both the case expression and case items as don’t-care conditions. While it offers flexibility, it may lead to unintended matches and should be used with caution.

Example: Case Statement in System Verilog

Let’s consider a simple 4-bit ALU (Arithmetic Logic Unit) operation selector. Depending on the operation code (opcode), the ALU will perform one of several operations.

module ALU(
    input logic [3:0] opcode,
    input logic [7:0] A,
    input logic [7:0] B,
    output logic [7:0] result
);
    always_comb begin
        case (opcode)
            4'b0000: result = A + B;      // Addition
            4'b0001: result = A - B;      // Subtraction
            4'b0010: result = A & B;      // AND operation
            4'b0011: result = A | B;      // OR operation
            4'b0100: result = ~A;         // NOT operation
            default: result = 8'b00000000; // Default to zero
        endcase
    end
endmodule

Testbench:

module ALU_tb;

  // Testbench signals
  logic [3:0] opcode;
  logic [7:0] A, B;
  logic [7:0] result;

  // Instantiate the ALU module
  ALU dut (
    .opcode(opcode),
    .A(A),
    .B(B),
    .result(result)
  );

  // Test procedure
  initial begin
    // Test addition
    opcode = 4'b0000;
    A = 8'h0A;  // 10 in decimal
    B = 8'h05;  // 5 in decimal
    #10;
    $display("Addition: A = %0d, B = %0d, Result = %0d", A, B, result);

    // Test subtraction
    opcode = 4'b0001;
    A = 8'h0A;  // 10 in decimal
    B = 8'h05;  // 5 in decimal
    #10;
    $display("Subtraction: A = %0d, B = %0d, Result = %0d", A, B, result);

    // Test AND operation
    opcode = 4'b0010;
    A = 8'b11001100;
    B = 8'b10101010;
    #10;
    $display("AND: A = %b, B = %b, Result = %b", A, B, result);

    // Test OR operation
    opcode = 4'b0011;
    A = 8'b11001100;
    B = 8'b10101010;
    #10;
    $display("OR: A = %b, B = %b, Result = %b", A, B, result);

    // Test NOT operation
    opcode = 4'b0100;
    A = 8'b11001100;
    B = 8'h00;  // B is irrelevant for NOT operation
    #10;
    $display("NOT: A = %b, Result = %b", A, result);

    // Test default case
    opcode = 4'b1111;  // Invalid opcode
    A = 8'h0A;
    B = 8'h05;
    #10;
    $display("Default case: A = %0d, B = %0d, Result = %0d", A, B, result);

    // End of simulation
    $stop;
  end

endmodule

Output:

Addition: A = 10, B = 5, Result = 15
Subtraction: A = 10, B = 5, Result = 5
AND: A = 11001100, B = 10101010, Result = 10001000
OR: A = 11001100, B = 10101010, Result = 11101110
NOT: A = 11001100, Result = 00110011
Default case: A = 10, B = 5, Result = 0

Best Practices for Using Case Statements

  • Default Case: Always include a default case to handle unexpected values.
  • Avoid Ambiguity: Ensure no overlapping or conflicting case items.
  • Casez and Casex: Use these carefully, as their pattern-matching abilities can lead to unintended behavior.
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