Disable iff and ended construct in assertions

disable iff in Assertions

The disable iff construct in SystemVerilog is used to conditionally disable an assertion. When the condition specified in disable iff evaluates to true, the assertion is disabled, and no failure will be reported, regardless of the assertion’s outcome.

Syntax

assert property (disable iff (condition) property_expression);

How It Works

  • Condition (disable iff): Specifies when the assertion should be disabled.
  • Property Expression: Defines the behavior to be monitored and validated when the assertion is active.

When the condition in disable iff is true, the assertion is temporarily ignored.

Example: Assertion with disable iff

Scenario

You want to monitor that the data_ready signal is asserted within 5 clock cycles after req is asserted. However, the assertion should be ignored if the reset signal is active.

property data_ready_check;
    @(posedge clk) disable iff (reset)
    req |-> ##[1:5] data_ready;
endproperty

// Assertion with disable iff
assert property (data_ready_check)
    else $error("Data was not ready within 5 cycles after request");

Explanation

  • The property data_ready_check ensures that data_ready must assert within 1 to 5 cycles after req.
  • The disable iff construct disables the assertion when reset is active. This prevents false failures during a reset condition.

ended Construct in Sequences

The ended construct in System Verilog is used to determine if a sequence has successfully completed. It returns a boolean value (true or false) based on whether the sequence has finished execution.

Syntax

sequence_name.ended

The .ended construct is typically used in properties or in conjunction with other sequences.

Example: Using ended in a Sequence

Scenario

You want to monitor that a sequence monitoring a handshake protocol (request followed by acknowledgment) completes successfully before issuing another request.

sequence handshake_seq;
    @(posedge clk) req ##[1:5] ack;
endsequence

property handshake_check;
    @(posedge clk) disable iff (reset) (handshake_seq.ended |-> req);
endproperty

// Assertion for handshake
assert property (handshake_check)
    else $error("New request issued before the previous handshake completed");

Explanation

  • The sequence handshake_seq monitors a handshake, ensuring ack is asserted within 1 to 5 cycles after req.
  • The .ended construct checks if the previous handshake sequence has completed before allowing a new req.
  • The disable iff ensures this check is ignored during reset.
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