# VLSI Worlds

> A Place For VLSI


## Posts

- [What are register generator tools and how they help VLSI Engineers](https://vlsiworlds.com/what-are-register-generator-tools-and-how-they-help-vlsi-engineers/): Designing and verifying a modern ASIC or SoC involves much more than writing RTL for the main data path and control logic. Almost every IP block needs a register interface that allows software, firmware, or another processor to configure and monitor the hardware. A typical register specification contains register names, addresses, offsets, fields, bit positions, access permissions, reset values, and descriptions. From this information, multiple engineering teams need to create their own implementation artifacts: Creating and maintaining all these artifacts manually is repetitive, time-consuming, and prone to errors. This is where a register generator tool becomes valuable. What Is a Register ... Read more
- [IP Verification vs. SOC Verification in VLSI](https://vlsiworlds.com/ip-verification-vs-soc-verification-in-vlsi/): In the world of Very Large-Scale Integration (VLSI), verification plays a pivotal role in ensuring that designs meet their functional and performance goals. Two prominent verification processes—IP verification and SOC verification—are critical steps in chip design. While they share the goal of functional correctness, they differ in scope, complexity, challenges, and methodologies. This article delves into the distinctions between IP and SOC, their verification processes, challenges, and future directions in the semiconductor industry. Understanding IP and SOC Key Differences Between IP and SoC Feature IP (Intellectual Property) SoC (System on Chip) Scope A single functional block/module A complete system integrated on ... Read more
- [ASIC Design Flow in VLSI](https://vlsiworlds.com/asic-design-flow-in-vlsi/): The world of electronics is heavily reliant on Application-Specific Integrated Circuits (ASICs) for delivering tailored, high-performance solutions. ASIC design is a cornerstone of Very-Large-Scale Integration (VLSI), enabling the integration of millions or even billions of transistors on a single chip. Understanding the ASIC design flow is crucial for professionals and enthusiasts in this domain. What is ASIC Design? ASICs are custom-designed integrated circuits intended for a specific application or product. Unlike general-purpose ICs, ASICs are optimized for dedicated tasks, offering benefits like enhanced performance, lower power consumption, and reduced size. They are commonly used in consumer electronics, automotive systems, telecommunications, and ... Read more
- [Formal Verification vs. Functional Verification](https://vlsiworlds.com/formal-verification-vs-functional-verification/): Verification is a critical phase in the design and development of Very Large-Scale Integration (VLSI) circuits. Ensuring the design meets its specifications and is free of functional defects is vital to avoid costly errors in silicon. The two primary methods used in the VLSI industry for this purpose are formal verification and functional verification. Both approaches have unique roles, advantages, and methodologies, yet they are often complementary. What is Formal Verification? Formal verification is a mathematically rigorous method that proves or disproves the correctness of a design concerning a given specification. It involves expressing the design and its intended properties in ... Read more
- [Steps for build a carrier in VLSI](https://vlsiworlds.com/steps-for-build-a-carrier-in-vlsi/): So, Here we are. Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI is a broad spectrum of technologies and there are several sub-categories of jobs for which company hire. Some categories are: Front-Design Engineers Verification Engineers Physical Designers (Back End) DFT Engineers FPGA Designers etc. There are plenty of VLSI companies in India where you can get a job according to your skills. Most of the companies offer internship and on the basis of your performance it can convert into full time offers. There are many ways ... Read more

## Pages

- [this keyword in system verilog](https://vlsiworlds.com/system-verilog/this-keyword-in-system-verilog/): The this keyword refers to the current instance of a class. It is used primarily in the following situations: It is particularly useful when there is ambiguity between class properties and function arguments, or when you want to emphasize that a particular variable belongs to the class instance. Syntax The this keyword is followed by the name of the property or method: Example 1: Resolving Naming Conflicts When a function or task argument has the same name as a class property, the this keyword resolves ambiguity by explicitly referring to the class property. Explanation: Output: Example 2: Calling Methods Explicitly The ... Read more
- [Implication and If else in constraints](https://vlsiworlds.com/system-verilog/implication-and-if-else-in-constraints/): Implication Constraints (-> Operator) The implication operator (->) is used to define conditional constraints. It ensures that when a specific condition is true, another condition or constraint must hold. The implication operator works like an if-then statement but in constraint form. Syntax: If the condition is false, the solver ignores the consequence, and the randomization continues without enforcing it. Example 1: Basic Implication Constraint Let’s consider a scenario where if a packet is marked as high state, its size must be greater than or equal to 200. Output: If-Else Constraints in SystemVerilog SystemVerilog also supports if-else constraints, which behave similarly to ... Read more
- [Iterative Constraints (foreach loop in constraint)](https://vlsiworlds.com/system-verilog/iterative-constraints-foreach-loop/): In System Verilog, iterative constraints allow you to apply constraints across arrays or collections of variables using iteration constructs like foreach. Iterative constraints simplify the process of defining conditions for multiple elements in an array, ensuring that constraints are clean, concise, and scalable. System Verilog provides the foreach loop, which can be used inside the constraint block to iterate over elements of an array. Key Features: Syntax: array_name refers to the array being constrained.i is the iterator that represents the index of the array element.The condition specifies the rule to apply to each array element. Example 1: Constraining All Elements to ... Read more
- [Functions in constraints](https://vlsiworlds.com/system-verilog/functions-in-constraints/): System Verilog allows the use of functions within constraints. By incorporating functions, you can encapsulate complex logic, improve readability, and ensure that constraints are maintainable and modular. Why Use Functions in Constraints? Using functions within constraints offers several advantages: Rules for Using Functions in Constraints When using functions within constraints, certain rules and guidelines must be followed: Syntax of Functions in Constraints You define a function as usual in System Verilog and then use it in the constraint block. Example 1: Range Constraint with a Function Let’s start with a simple example where a function computes a range dynamically based on ... Read more
- [Unique constraint](https://vlsiworlds.com/system-verilog/unique-constraint/): The unique constraint ensures that all variables in a list or elements to an array are assigned distinct (non-overlapping) values during randomization. If it is impossible to satisfy the uniqueness condition due to other constraints or limited ranges, the randomization attempt will fail. Syntax: How It Works Example 1: Unique IDs for a Group Let’s consider a scenario where we need to assign unique IDs to a group of elements. Explanation: Output: Example 2: Unique Priorities for Tasks Imagine a scenario where we have multiple tasks, and each task must be assigned a unique priority level. Explanation: Output: Advantages of Using ... Read more
- [Abstract Class and Pure Virtual methods](https://vlsiworlds.com/system-verilog/abstract-class-and-pure-virtual-methods/): What Is an Abstract Class? An abstract class is a class that serves as a base class and cannot be instantiated directly. It acts as a template for other classes, defining methods and properties that derived (child) classes must implement or extend. Abstract classes are often used to enforce a standard structure in testbenches or verification components. Characteristics of Abstract Classes: Declaring an Abstract Class: To make a class abstract in System Verilog, you use the keyword virtual before the class declaration. Pure Virtual Methods in Abstract Classes A pure virtual method is a method declared in an abstract class that ... Read more
- [solve before constraint](https://vlsiworlds.com/system-verilog/solve-before-constraint/): The solve…before construct in System Verilog allows you to specify the order in which the constraint solver resolves variables during randomization. It does not impose a hard constraint on the values of the variables but ensures that the solver determines the value of one variable before another. Syntax: This means that during randomization: Example: Dependent Variables (without solve before) Let’s consider a scenario where we have two variables, x and y. The value of y should always be twice the value of x. Output: Same example with solve before: Output: Explanation: Why Use Solve-Before Constraints?
- [Bidirectional Constraint](https://vlsiworlds.com/system-verilog/bidirectional-constraint/): A bidirectional constraint ensures that two or more variables satisfy a relationship that is valid regardless of which variable is assigned first. For example, if you have two variables A and B with the constraint A + B == 100, randomization will generate values for A and B such that their sum equals 100. Either A or B can be set first, and the other will adjust accordingly to satisfy the constraint. Bidirectional constraints are naturally supported in System Verilog because of its powerful constraint-solving engine. There is no need for special syntax; they are created by defining constraints that establish ... Read more
- [Soft Constraints](https://vlsiworlds.com/system-verilog/soft-constraints/): In System Verilog, soft constraints are a powerful feature used to provide default or preferred values during randomization without enforcing them strictly. They allow the randomization process to use the default constraint values only when no other constraints (hard constraints or conflicting conditions) override them. This flexibility is beneficial in scenarios where certain values are desirable but not mandatory. What Are Soft Constraints? Soft constraints in SystemVerilog are defined using the soft keyword within a constraint block. These constraints act as recommendations or preferences, and the randomization engine will attempt to honor them. However, if hard constraints or other conditions make ... Read more
- [System Verilog Distribution Constraints](https://vlsiworlds.com/system-verilog/system-verilog-distribution-constraints/): In SystemVerilog, distribution constraints allow precise control over the randomization of variables by assigning weights to specific values or ranges of values. The dist operator is central to this capability, with two forms := and :/ each offering distinct ways of distributing weights. This article explains the difference between the := and :/ operators, how they work with values and ranges, and provides examples to illustrate their behavior in real-world scenarios. Overview of the dist Operator The dist operator is used in constraints to assign weights to values or ranges. The value and weights can be constant or variables. This determines ... Read more
- [Inside operator in Constraints](https://vlsiworlds.com/system-verilog/inside-operator-in-constraints/): In SystemVerilog, the inside operator is a powerful tool used within constraints to specify that a random variable’s value should belong to a particular set of values or ranges. It simplifies constraint writing, making it easier to handle scenarios where specific patterns or groups of values are required. This article delves into the inside operator, its syntax, usage scenarios, and examples, showcasing how it can streamline constraint-based randomization. What is the inside Operator? The inside operator checks whether a value is part of a specified set or range. It is commonly used in constraints to define permissible values for a random ... Read more
- [Inline Constraints](https://vlsiworlds.com/system-verilog/inline-constraints/): SystemVerilog is widely used for functional verification, and its constraint-based randomization is a powerful feature that allows the generation of random values while meeting specific requirements. Constraints can be defined inside a class or applied inline when calling the randomize() method. Inline constraints provide flexibility for overriding or adding constraints temporarily without modifying the class itself. This article explores inline constraints, their usage, scenarios involving conflicts, and how constraints from the class and inline constraints interact. We’ll use examples to illustrate these concepts. Inline Constraints Inline constraints are constraints written directly within the randomize() method call. They are used to override ... Read more
- [Class Constructors in System Verilog](https://vlsiworlds.com/system-verilog/class-constructors-in-system-verilog/): In SystemVerilog, constructors play a vital role in object-oriented programming. They are special methods used to initialize objects of a class and assign initial values to their properties when the object is created. Without constructors, initializing class properties after object creation would require additional code, making the design less efficient and prone to errors. This article explores how constructors work in System Verilog, explains their significance, and provides examples to illustrate their usage. What is a Constructor? A constructor in SystemVerilog is a special method named new(). It is automatically called when an object of the class is instantiated using the ... Read more
- [Classes in System Verilog](https://vlsiworlds.com/system-verilog/classes-in-system-verilog/): System Verilog introduced Object-Oriented Programming (OOP) concepts to enhance its capabilities for designing and verifying complex systems. Classes are a cornerstone of these OOP features, providing a way to encapsulate data (properties) and functions (methods) together. In this article, we’ll discuss how to declare a class, create objects, and access properties and methods in System Verilog, with practical examples to clarify each concept. What is a Class in SystemVerilog? A class in SystemVerilog is a blueprint for creating objects. It defines: Classes support inheritance, polymorphism, and other OOP principles, making them highly versatile for verification purposes, especially in UVM (Universal Verification ... Read more
- [Blocking and non-blocking assignments](https://vlsiworlds.com/system-verilog/blocking-and-non-blocking-assignments/): In Verilog, blocking (=) and non-blocking (<=) assignments are fundamental concepts that play a critical role in defining the behavior of your code. Misunderstanding these assignments can lead to unexpected simulation results, making it vital for designers to grasp their differences and proper usage. This article dives into the key distinctions between the two assignment types and provides examples to clarify their applications. What are Blocking Assignments? Blocking assignments, represented by the = operator, execute sequentially. Each assignment must complete before the next one begins. This sequential behavior resembles traditional programming languages and is ideal for modeling combinational logic in Verilog. ... Read more
- [Random System Methods in SV](https://vlsiworlds.com/system-verilog/random-system-methods-in-sv/): SystemVerilog offers a variety of tools for generating random numbers, which are essential for testbench design in constrained random verification (CRV). Among these tools, the random system methods—$random, $urandom, and $random_range()—provide flexible and straightforward ways to generate random values for diverse use cases. In this article, we’ll dive deep into each of these methods, understand their differences, and explore practical examples to illustrate their applications. 1. $random: The Classic Random Number Generator The $random system function is the traditional random number generator in SystemVerilog. It generates a signed 32-bit random integer. Syntax Characteristics Example Output: Limitations 2. $urandom: The Unsigned Alternative ... Read more
- [Assertion Tutorial](https://vlsiworlds.com/system-verilog/assertion-tutorial/)
- [Static constraints](https://vlsiworlds.com/system-verilog/static-constraints/): The static keyword can be employed in particular scenarios where you want to define constraints that are independent of object instances. The static keyword in SystemVerilog serves two main purposes: When used in constraints, static ensures that the constraint is evaluated in a context not tied to an object instance. This is useful in scenarios where constraints depend on global or shared data rather than the internal state of an object. Syntax of static Constraints The static keyword is used within the constraint block. The syntax follows the structure: The static constraint block can include any logic or condition, but it ... Read more
- [constraint mode](https://vlsiworlds.com/system-verilog/constraint-mode/): What is Constraint Mode? Constraint mode in System Verilog allows you to enable or disable specific constraints dynamically during simulation. By default, all constraints in a class are active, but certain scenarios may require selective activation of constraints to create specific test conditions. This is achieved using the constraint_mode() system function. Example of Constraint Mode Let’s illustrate the use of constraint mode with an example: Explanation: Output:
- [Polymorphism in System Verilog](https://vlsiworlds.com/system-verilog/polymorphism-in-system-verilog/): Polymorphism is a cornerstone of object-oriented programming (OOP) and plays a vital role in SystemVerilog’s ability to build scalable and reusable verification environments. In SystemVerilog, polymorphism allows objects to take multiple forms depending on their context. This enables flexible and efficient management of complex verification scenarios. What is Polymorphism? Polymorphism refers to the ability of a variable, function, or method to process objects of different types in a uniform manner. In SystemVerilog, polymorphism is typically achieved through virtual methods and dynamic object handling, where a base class reference can point to an object of any derived class. Polymorphism simplifies testbench development ... Read more
- [System Verilog Constraints and Constraints Inheritance](https://vlsiworlds.com/system-verilog/constraints-in-system-verilog-2/): In hardware verification, the ability to generate randomized test scenarios is essential for thorough testing. System Verilog offers constraints to control the randomization process, ensuring generated values meet specific requirements while maintaining flexibility. This article explores the concept of constraints in System Verilog, focusing on constraint inheritance, a powerful feature for hierarchical and reusable verification environments. What are Constraints? Constraints in SystemVerilog are rules or conditions that dictate the range or relationships of random values generated for variables. They help ensure that the randomized test scenarios are realistic and conform to the design requirements. SystemVerilog constraints are declared using the constraint ... Read more
- [Constraints Tutorial](https://vlsiworlds.com/system-verilog/constraints-in-system-verilog/)
- [System Verilog Introduction](https://vlsiworlds.com/system-verilog/system-verilog-introduction/): SystemVerilog was officially launched in 2002. It was introduced as an extension of Verilog-2001 to enhance the capabilities of the Verilog language by adding advanced features for hardware design and verification. Here’s a brief timeline of SystemVerilog’s evolution: SystemVerilog is now widely used in the semiconductor industry for digital design and verification, and it is the foundation for advanced methodologies like UVM (Universal Verification Methodology). Why SystemVerilog? While Verilog is efficient for modeling hardware at the register-transfer level (RTL), it lacks the sophistication required for verifying complex designs. SystemVerilog addresses these limitations by combining Verilog’s hardware modeling strengths with robust features ... Read more
- [Encapsulation and Data Hiding in System Verilog](https://vlsiworlds.com/system-verilog/encapsulation-and-data-hiding-in-system-verilog/): SystemVerilog, with its object-oriented programming (OOP) features, introduces powerful mechanisms like encapsulation and data hiding to enhance code modularity, security, and reusability. These concepts are crucial for managing complexity in verification environments and ensuring that designs are robust and maintainable. In this article, we will explore encapsulation and data hiding in System Verilog, along with practical examples to illustrate the use of the local and protected keywords. What is Encapsulation? Encapsulation is the bundling of data (variables) and methods (functions and tasks) into a single unit, such as a class. It controls access to the internal workings of a class and ... Read more
- [Virtual Methods in System Verilog](https://vlsiworlds.com/system-verilog/virtual-methods-in-system-verilog/): The virtual keyword in SystemVerilog is used to declare methods and interfaces that support polymorphism. It allows a derived class to override methods from a base class, enabling dynamic binding at runtime. Without the virtual keyword, method binding is static, determined at compile time. Where is the virtual Keyword Used? The virtual keyword is primarily used in two contexts: Let’s explore these applications in detail. 1. Virtual Methods A method marked with virtual allows derived classes to override its behavior, enabling runtime polymorphism. This is particularly useful in verification environments, where you might want different behaviors depending on the object type ... Read more
- [System Verilog Scope Resolution Operator ::](https://vlsiworlds.com/system-verilog/system-verilog-scope-resolution-operator/): The :: operator in SystemVerilog allows you to reference identifiers (such as variables, constants, functions, tasks, and types) within a specific scope. It helps to distinguish between identifiers with the same name but residing in different scopes. Common use cases of the :: operator include: Examples of the Scope Resolution Operator in Action: 1. Accessing Class Static Members In SystemVerilog, static members of a class belong to the class itself rather than an instance. The :: operator is used to access these members directly through the class name. Example: Static Members: Output: Here, MyClass::static_var and MyClass::display() demonstrate how the :: operator ... Read more
- [Super Keyword](https://vlsiworlds.com/system-verilog/super-keyword/): The super keyword in SystemVerilog is a powerful feature of object-oriented programming (OOP) that allows derived classes to access properties and methods of their parent (or base) class. It provides a mechanism to enhance code reusability and maintainability by facilitating clear and organized inheritance structures. This article explores the super keyword in SystemVerilog with detailed explanations and examples to help you integrate it effectively into your design verification projects. What is the super Keyword? In SystemVerilog, the super keyword is used within a derived class to: By using super, you can extend or modify the behavior of inherited methods and ensure ... Read more
- [Scheduling Regions in System Verilog](https://vlsiworlds.com/system-verilog/scheduling-regions-in-system-verilog/): SystemVerilog, as a hardware description and verification language, provides a well-defined event-driven simulation scheduling mechanism. This mechanism is based on scheduling regions, which dictate the order and timing of operations during simulation. Scheduling regions are critical for ensuring deterministic behavior and accurate representation of hardware designs. In this article, we’ll explore the various scheduling regions in SystemVerilog and understand their roles and functions. SystemVerilog’s simulation engine is event-driven, meaning operations are triggered by changes in signals or conditions. The simulation time is divided into time steps, and within each time step, events are processed in a predefined sequence across several regions. ... Read more
- [System Verilog Events](https://vlsiworlds.com/system-verilog/system-verilog-events/): System Verilog events are powerful synchronization constructs that allow processes to communicate and coordinate effectively. Events play a crucial role in both design and verification, enabling precise control of the timing and sequencing of actions. This article provides an in-depth exploration of events, including triggering with -> and ->>, waiting for events using @ and wait, and leveraging the wait_order() method for ordered synchronization. 1. Understanding Events in SystemVerilog An event in SystemVerilog is a handle used to signal and wait for specific occurrences in the simulation. Events do not hold any value or state, and they do not persist after ... Read more
- [Shallow Copy and Deep Copy](https://vlsiworlds.com/system-verilog/shallow-copy-and-deep-copy/): In SystemVerilog, copying objects is a common requirement when working with classes and dynamic data structures. However, the distinction between shallow copy and deep copy is critical for correctly handling memory and avoiding unexpected behavior. This article explains the concepts of shallow and deep copies in SystemVerilog, supported by examples for clarity. In SystemVerilog: Let’s use a class with a nested object to demonstrate shallow and deep copying effectively. Defining Classes with Nested Objects Here, we define a Transaction class that contains a nested object Metadata. Shallow Copy Example In a shallow copy, a new object is created, but the nested ... Read more
- [Digital Electronics Interview Questions](https://vlsiworlds.com/interview-guide/digital-electronics-interview-questions/)
- [wait-fork and disable-fork](https://vlsiworlds.com/system-verilog/wait-fork-and-disable-fork/): SystemVerilog provides advanced constructs to manage concurrency and synchronization in testbenches and hardware design. Two powerful constructs in this context are wait-fork and disable-fork. These constructs are especially useful for managing processes running within fork...join blocks. Let’s explore their functionality with detailed explanations and examples. The Need for wait-fork and disable-fork In some scenarios, you might want to: wait-fork The wait-fork construct suspends the parent process until all child threads spawned by fork…join have completed. It’s particularly useful when you use fork…join_none or fork…join_any, where the parent process doesn’t inherently wait for all child processes to finish. Example: Output: In this ... Read more
- [UVM Interview Questions](https://vlsiworlds.com/interview-guide/uvm-interview-questions/)
- [System Verilog Interview Questions](https://vlsiworlds.com/interview-guide/system-verilog-interview-questions/)
- [Understanding Fork-Join Constructs in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-fork-join-constructs-in-systemverilog/): SystemVerilog, a powerful hardware description and verification language, introduces advanced constructs to manage parallel processes effectively. Among these, fork-join, fork-join_any, and fork-join_none are pivotal for controlling multiple threads. This article delves into these constructs, explaining their behavior with practical examples. What is Fork-Join? fork-join is used to execute multiple processes in parallel. All threads within the fork-join block must complete before the program continues execution beyond the block. Syntax: In fork_join, once all the processes inside the block will be completed, only after that it will come out of the block. Example: Output: In this example, the simulation waits for all three threads to complete before moving to ... Read more
- [Argument Passing and the const Keyword in SystemVerilog](https://vlsiworlds.com/system-verilog/argument-passing-and-the-const-keyword-in-systemverilog/): SystemVerilog allows flexible argument-passing mechanisms in functions and tasks, enabling efficient and controlled communication between modules, tasks, and functions. Among these, pass by value and pass by reference play crucial roles in determining how data is passed and manipulated. Additionally, the const keyword adds another layer of control by ensuring immutability for certain arguments. This article explores pass by value, pass by reference, and the const keyword in SystemVerilog, using practical examples to clarify their usage and benefits. Argument Passing in SystemVerilog Arguments in SystemVerilog can be passed to tasks and functions using two main methods: 1. Pass by Value When ... Read more
- [Task and Functions](https://vlsiworlds.com/system-verilog/task-and-functions/): Both tasks and functions allow you to encapsulate logic into named blocks, which can then be invoked multiple times. They simplify code by eliminating redundancy, enhancing readability, and enabling modular design. They allow engineers to encapsulate frequently used code sequences, making designs and testbenches more organized and easier to debug. While they share similarities, tasks and functions serve distinct purposes and have specific rules for their usage. Tasks in SystemVerilog A task is used for operations that may: Syntax and Example: Key Characteristics of Tasks: Example with Timing Control: Output: Functions in SystemVerilog A function is used for pure combinational operations ... Read more
- [Clocking Blocks and Modports](https://vlsiworlds.com/system-verilog/clocking-blocks-and-modports/): Clocking Blocks in SystemVerilog A clocking block in System Verilog is a construct that simplifies and synchronizes signal interactions with a clock edge. It provides a clean way to specify the timing relationship between input and output signals in a testbench. Additionally, the clocking skew feature within clocking blocks provides fine-grained control over signal sampling and driving relative to a clock edge. Clocking skew defines when signals are sampled or driven relative to the clock edge. This feature is critical for ensuring timing correctness in designs where the sampling and driving windows need precise alignment. Why Use Clocking Blocks? Syntax of ... Read more
- [Interface and Virtual Interface in SystemVerilog](https://vlsiworlds.com/system-verilog/interface-and-virtual-interface-in-systemverilog/): An interface in SystemVerilog is a construct that bundles together a set of signals and functionality into a single logical entity. This abstraction simplifies the connections between modules by reducing the need for numerous port declarations and wiring in a design. We can also declare task or functions inside the interface. Key Features of an Interface: Defining and Using an Interface Here’s an example of defining an interface: Connecting an Interface to a Module To use the interface in a design: Testbench: Output: What is a Virtual Interface in System Verilog? A virtual interface is a pointer to an interface instance. ... Read more
- [Coverage Tutorial](https://vlsiworlds.com/system-verilog/coverage-in-system-verilog/)
- [Exploring Coverage Options in SystemVerilog](https://vlsiworlds.com/system-verilog/exploring-coverage-options-in-systemverilog/): Functional coverage is a critical aspect of hardware verification, allowing engineers to validate whether all intended design functionalities are exercised during simulation. SystemVerilog provides a wide range of coverage options to control and customize the behavior of functional coverage. These options empower engineers to fine-tune their coverage collection, exclude irrelevant scenarios, and focus on critical conditions. In this article, we’ll explore the key coverage options available in SystemVerilog and how they can be used effectively. Key Coverage Options in SystemVerilog 1. option.weight The option.weight setting allows you to assign a weight to a covergroup or coverpoint. By default, all coverage points ... Read more
- [Coverage Methods in SystemVerilog](https://vlsiworlds.com/system-verilog/coverage-methods-in-systemverilog/): Key Coverage Methods in SystemVerilog 1. void sample() The sample() method is one of the most fundamental tools in a covergroup. It triggers the evaluation of all coverpoints and cross coverage within the associated covergroup. By default, sampling occurs when covergroup variables are assigned new values during a simulation, but you can manually call sample() to control when coverage is collected. Example: In this example: 2. void set_inst_name(string name) The set_inst_name() method assigns a unique name to a specific instance of a covergroup. This is particularly useful in simulations where multiple instances of the same covergroup are created, as it helps ... Read more
- [Understanding Cross Coverage in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-cross-coverage-in-systemverilog/): Cross coverage is a mechanism in SystemVerilog used to analyze how multiple coverage points interact with each other. It is particularly useful when you want to check combinations of values across different variables. For example, if you have two variables, opcode and status, cross coverage ensures you verify all possible pairs of their values. By leveraging cross coverage, you can detect whether your simulation exercises specific combinations of parameters, which may represent critical scenarios for the design under test. Defining Cross Coverage in SystemVerilog Cross coverage is typically defined within a covergroup. Here’s a basic example: In this snippet: Benefits of ... Read more
- [Understanding `define, parameter, and localparam in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-define-parameter-and-localparam-in-systemverilog/): In SystemVerilog, controlling constants and configuring modules efficiently is key to writing clean, reusable, and maintainable code. Three important constructs—`define, parameter, and localparam—help us define constant values and control configuration in our designs. Each serves a different purpose and has unique characteristics. This article explores these constructs, explaining when and how to use each with examples. Understanding `define, parameter, and localparam in SystemVerilog In SystemVerilog, controlling constants and configuring modules efficiently is key to writing clean, reusable, and maintainable code. Three important constructs—`define, parameter, and localparam—help us define constant values and control configuration in our designs. Each serves a different purpose ... Read more
- [Understanding SystemVerilog DPI (Direct Programming Interface)](https://vlsiworlds.com/system-verilog/understanding-systemverilog-dpi-direct-programming-interface/): SystemVerilog’s Direct Programming Interface (DPI) is a powerful feature that allows you to integrate SystemVerilog with foreign programming languages like C and C++. DPI enables the import and export of functions between SystemVerilog and these external languages, allowing developers to reuse existing software models, execute complex computations, or interact with low-level system resources that are better suited to a software language. This flexibility makes DPI essential in scenarios where mixed-language simulation or specialized processing is required in a testbench or hardware model. Basics of SystemVerilog DPI SystemVerilog DPI is built around two core concepts: The DPI uses import and export directives ... Read more
- [Callbacks in System Verilog](https://vlsiworlds.com/system-verilog/understanding-callbacks-in-systemverilog/): What is a Callback? A callback is a function or task defined in one part of the code but called from another. Callbacks allow additional functionality to be “hooked” into a component at runtime without modifying the core code. In verification environments, callbacks are typically used to customize or add behavior, such as injecting errors or altering data flow, for specific test cases. For example, in a System Verilog testbench, a callback might be used to alter the behavior of a driver, monitor, or checker in different simulation scenarios. This approach keeps the main component code clean and general, while allowing ... Read more
- [Structures and Unions in System Verilog](https://vlsiworlds.com/system-verilog/structures-and-unions-in-system-verilog/): Structures in SystemVerilog A structure in SystemVerilog is a user-defined composite data type that groups variables of different data types under a single name. It is similar to structs in C or C++. Each variable in a structure is called a member or field. The key feature of a structure is that each field has its own memory space, meaning they do not overlap. Declaring a Structure To declare a structure, use the struct keyword, followed by the list of data fields and their types. Each field has a name and a type, allowing different types of data to be grouped ... Read more
- [Understanding Data Types in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-data-types-in-systemverilog/): SystemVerilog is a powerful hardware description and verification language that builds on the foundations of Verilog, adding several features for better modeling, design, and verification. One of the essential aspects of SystemVerilog is its wide variety of data types, which allows designers to represent and manipulate a diverse range of data. This article will explore the different data types available in SystemVerilog, including simple data types, composite types, and specialized types, helping you choose the right type for your needs. Basic Data Types in SystemVerilog SystemVerilog supports several simple data types, including integer, real, and string types, which are fundamental to ... Read more
- [Array Manipulation Methods in SystemVerilog](https://vlsiworlds.com/system-verilog/array-manipulation-methods-in-systemverilog/): System Verilog offers several built-in methods to work with arrays. These methods can be applied to static, dynamic arrays and queue, providing flexibility in managing data. Here’s a look at each of these methods and how they work: 1. find() and find_index() Methods The find method searches for elements in an array that satisfy a given condition and returns them in a new array. The find_index method, similarly, returns an array of indices of elements that match the condition. The with keyword in System Verilog is used in conjunction with array methods like find and find_index to specify the condition or ... Read more
- [Queues in SystemVerilog](https://vlsiworlds.com/system-verilog/queues-in-systemverilog/): In SystemVerilog, a queue is a variable-size, indexed data structure that can grow or shrink as elements are added or removed. Unlike fixed-size arrays, queues are highly flexible, making them an ideal choice for implementing FIFO (First-In, First-Out) structures and various temporary storage needs in verification environments. This data structure allows for dynamic resizing, enabling easy addition and removal of elements, which makes it especially suitable for applications where the number of stored items may vary during runtime. A queue in SystemVerilog is defined as follows: Here, data_type is the type of elements that the queue will hold, and $ indicates ... Read more
- [Understanding Mailboxes in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-mailboxes-in-systemverilog/): A mailbox in SystemVerilog is a type of object used for inter-process communication. It allows one process to place data into the mailbox and another process to retrieve it. This makes mailboxes ideal for coordinating tasks between parallel processes, especially in testbenches where one component might generate data while another component consumes it. Some key points about mailboxes in SystemVerilog: Declaring and Creating a Mailbox In SystemVerilog, a mailbox is declared as a mailbox type and created using the new constructor. You can specify an integer argument in the constructor to limit the capacity of the mailbox, making it bounded. If ... Read more
- [Shift Operators in SystemVerilog](https://vlsiworlds.com/system-verilog/shift-operators-in-systemverilog/): Shift operators in SystemVerilog move the bits of a variable or constant either to the left or right. They are primarily used for: The syntax for shift operators is straightforward: SystemVerilog distinguishes between logical and arithmetic shifts, each with its unique behavior. 1. Left Shift Operators in SystemVerilog The left shift operator shifts bits to the left, adding zeros on the right side. This action can be done logically or arithmetically, depending on the context. Logical Left Shift (<<) The logical left shift operator shifts bits to the left by a specified number of positions, inserting zeros into the least significant ... Read more
- [Semaphores in System Verilog](https://vlsiworlds.com/system-verilog/understanding-semaphores-in-systemverilog/): A semaphore in SystemVerilog is a synchronization object that manages a certain number of “keys.” These keys represent access to a shared resource. When a process needs to access the resource, it must first obtain one or more keys from the semaphore. If the required number of keys is available, the process is granted access; if not, the process waits until keys are released by other processes. Semaphores help in controlling the access of multiple processes to a shared resource, ensuring orderly and safe access to avoid race conditions and conflicts. Basic Semaphore Usage To use a semaphore in SystemVerilog: Example: ... Read more
- [UVM Phases](https://vlsiworlds.com/uvm/understanding-uvm-phases-in-systemverilog/): The Universal Verification Methodology (UVM) is widely used in the SystemVerilog verification community to create modular, reusable, and scalable testbenches for complex digital designs. One of UVM’s powerful features is its phasing mechanism, which organizes the simulation process into distinct phases, each designed for a specific part of the testbench operation. Understanding these UVM phases is essential for building efficient and synchronized testbenches. In this article, we will explore each of the UVM phases, explain their purpose, and discuss the order in which they are executed. Overview of UVM Phases In UVM, a phase represents a particular stage in the simulation ... Read more
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- [Dynamic and Associative Arrays in SystemVerilog: A Complete Guide](https://vlsiworlds.com/system-verilog/dynamic-and-associative-arrays-in-systemverilog-a-complete-guide/): In many verification environments, the size of the data to be handled is not always fixed. For example: For these scenarios, dynamic arrays and associative arrays are much more flexible than static or fixed-size arrays. Dynamic Arrays A dynamic array in SystemVerilog is an array whose size can be changed at runtime. This type of array is particularly useful when the number of elements is not known ahead of time. Dynamic arrays are declared without specifying the size initially, and their size can be adjusted later using the new[] method. Declaration of Dynamic Arrays Here, array[] is a dynamic array of ... Read more
- [Understanding Arrays in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-arrays-in-systemverilog/): Arrays are an essential part of SystemVerilog (SV), allowing designers and verification engineers to work with collections of variables in an efficient and structured way. SystemVerilog extends traditional Verilog arrays by adding features like dynamic arrays, associative arrays, and queues, which are useful in modern VLSI (Very Large Scale Integration) design and verification. In this article, we will dive deep into arrays in SystemVerilog, including multidimensional arrays, packed and unpacked arrays, and their usage in practical scenarios. What is an Array? In SystemVerilog, an array is a collection of variables of the same data type, stored in contiguous memory locations. Arrays ... Read more
- [Understanding Randomization in SystemVerilog](https://vlsiworlds.com/system-verilog/understanding-randomization-in-systemverilog/): Randomization is one of the key features in SystemVerilog, especially when it comes to functional verification. It allows verification engineers to create various randomized test scenarios that can explore edge cases and corner cases that might not be covered by directed testing. Randomized testing helps to identify bugs that could be missed otherwise, leading to more robust and comprehensive verification. In this article, we’ll explore the concept of randomization in SystemVerilog, the rand and randc keywords, different randomization modes, and key functions like pre_randomize and post_randomize. We’ll also look at how constraints help control randomization and make the process more efficient ... Read more
- [Understanding UVM Register Abstraction Layer (RAL)](https://vlsiworlds.com/uvm/understanding-uvm-register-abstraction-layer-ral/): The UVM Register Abstraction Layer (RAL) is one of the most critical components of the Universal Verification Methodology (UVM), aimed at simplifying the process of accessing and manipulating hardware registers during functional verification. In complex designs, hardware registers are used to control functionality, store configuration data, and communicate between different hardware blocks. Managing these registers manually can be error-prone and tedious, especially for large designs. This is where UVM RAL comes in to automate and streamline register access, making verification more efficient. In this article, we’ll dive deep into the UVM Register Abstraction Layer (RAL), its importance, and its various components ... Read more
- [Types of Coverage: Code and Functional in System Verilog](https://vlsiworlds.com/system-verilog/types-of-coverage-code-and-functional-in-system-verilog/): Coverage is a critical concept in System Verilog, especially in the verification domain of VLSI (Very Large Scale Integration) design. It plays an essential role in ensuring that the design being verified has been thoroughly tested and that all the functional aspects of the design are covered by the test cases. Coverage helps in identifying the untested areas of a design and provides confidence that the verification is exhaustive and accurate. In this article, we will explore the different types of coverage, specifically code coverage and functional coverage, as well as key System Verilog constructs like cove groups, bins, and the ... Read more
- [UVM Tutorial](https://vlsiworlds.com/uvm/): The Universal Verification Methodology (UVM) is a widely adopted framework in the world of functional verification for designing reusable and scalable testbenches. Developed to address the challenges of verifying complex System-on-Chip (SOC) designs, UVM standardizes verification methodologies, making it easier for teams to collaborate, reuse components, and enhance verification efficiency. It is a library of classes and utilities built on System Verilog. It provides a structured approach to verification by defining reusable components, facilitating consistent practices across projects and teams. This tutorial will explore the components, architecture, and benefits of UVM, making it an indispensable tool for modern VLSI verification.
- [System Verilog Tutorial](https://vlsiworlds.com/system-verilog/): System Verilog is a powerful hardware description and verification language that extends the capabilities of Verilog, a widely-used language in digital design and verification. Introduced as an enhancement to Verilog, System Verilog bridges the gap between hardware description and verification, making it an essential tool for modern hardware engineers. In this tutorial we will know each and everything about System Verilog.
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- [Interview Experience For XILINX](https://vlsiworlds.com/interview-guide/interview-experiences/interview-experience-for-xilinx/): This article is contributed by my friend. He is currently working in Xilinx as a Digital Design Engineer. The selection of candidates for interview was entirely based on resume. The interview consists of 3 rounds. Round 1 (Technical): The first round was entirely based on my resume. First they asked me to introduce yourself. After that the interview started. The interviewer asked me to explain all the MTech projects, that I have done and MTech Thesis. He also asked some cross questions regarding the projects. My suggestion for all the readers is Please read your resume thoroughly. This is the most ... Read more
- [Important Books/PDFs For VLSI](https://vlsiworlds.com/important-books-for-vlsi/): This section is for those engineering students who are unable to get hard copy of books due to some reasons. We are trying to help them by providing e-books and other study materials with free of cost. But if you are really serious about study, we will suggest you to buy the books from publishers or shops or commercial websites. The given books/PDFs are already available on the internet. VLSI WORLDS does not own any of this book or pdf. We are just helping the students and graduates by providing important contents under a single roof. If you have any suggestions, ... Read more
- [Interview Experiences](https://vlsiworlds.com/interview-guide/interview-experiences/): “Knowledge is Power But Knowledge Without Action Is Useless.” Today VLSI is one of the most booming sector and Electronics Engineers try their best to make a career in this field. However, entry in semiconductor industry is a little different than any other field. If you are placed in your college time then well & good but Off campus placement is a little difficult due to a lot of competition and a large number of freshers. Here, we are bringing you a series of real interview experiences of different VLSI companies. We hope after reading theses experiences, you will get to ... Read more
- [Crosstalk Effect in VLSI](https://vlsiworlds.com/crosstalk-effect/): In VLSI sub-micron technology, due to scaling process the chip density is increasing day by day and respectively size of the transistors are reducing. The spaces between the wires are also decreasing and this causes many problems like short channel effect, signal crosstalk, heating problem etc.           Signal Crosstalk is a phenomenon in which the switching activity of a net wire affects the switching activity of its nearby wire because of coupling capacitance and inductance between the two nets. Crosstalk creates an undesired effect on the neighboring circuit or net which can affect the timing behavior of circuit or it can ... Read more
- [Latch up in CMOS and it's prevention](https://vlsiworlds.com/latch-up-in-cmos-and-its-prevention/): Latch up refers to a short circuit formed between power and ground pin in an IC leading to high current and damage to the IC. In CMOS transistor latch up is the phenomenon of low impedance path between power pin and ground pin due to interaction between parasitic PNP and NPN transistors. The structure formed by these resembles a Silicon Controlled rectifier(SCR). These form a positive feedback loop, short circuit the power and ground pin which eventually causes excessive current and can even permanently damage the device. Although the use of an epitaxial layer and other process improvements have lessened the ... Read more
- [Interview experience for Qualcomm](https://vlsiworlds.com/interview-guide/interview-experiences/interview-experience-for-qualcomm/): This article is contributed by my friend. He is currently working in Qualcomm as a hardware engineer. The interview process consists of total 4 rounds consisting of 1 online written test, 2 technical rounds and 1 HR round. The written test had 3 sections, Aptitude section, Technical Section and programming section. Each section had approximate 20 Questions. In technical section mostly questions were from digital electronics and digital CMOS. Programming section had questions from C language. All questions were multiple choice questions. Round 1(Technical)(Duration 45-50 Mins) : Q1) HR went through my resume and asked me the reason for my subsequently ... Read more
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- [Phase Raise Objection and Phase Drop Objection in UVM](https://vlsiworlds.com/uvm/phase-raise-objection-and-phase-drop-objection-in-uvm/): One of the most common questions UVM beginners (and even experienced engineers!) struggle with is: “Why is my simulation ending early?”“Why is my test stuck forever?” In most cases, the answer lies in phase objections. Why Do We Need Phase Objections in UVM? UVM is phase-driven. Every component goes through a sequence of predefined phases such as: Among these, runtime phases (like run_phase, main_phase, etc.) execute concurrently across all components. The problem is UVM does not know automatically when your stimulus, sequences, or checks are complete. That’s where objections come in. Objections tell the UVM scheduler: “Hey, I am still doing ... Read more
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- [Types of Ports in UVM TLM](https://vlsiworlds.com/uvm/types-of-ports-in-uvm-tlm/): In UVM (Universal Verification Methodology), TLM (Transaction Level Modeling) is used to transfer data between components using transactions instead of signals.To enable this communication, UVM defines three fundamental TLM connection types Three Types of TLM Connection Objects in UVM: UVM TLM communication is built using: These are not SystemVerilog ports — they are UVM class-based communication objects TLM Port A TLM port is used by a component to initiate a transaction. Constructor Method: Typical Usage TLM Export A TLM export acts as a forwarding interface. Constructor Method: Typical Usage TLM Implementation (Imp) A TLM imp provides the actual implementation of TLM ... Read more
- [UVM TLM Interface and Interface Class Method Types](https://vlsiworlds.com/uvm/uvm-tlm-interface-and-interface-class-method-types/): As we discussed in previous chapter, In UVM (Universal Verification Methodology), communication between verification components is done using Transaction Level Modeling (TLM). TLM-1 is a method-based transaction communication mechanism where data is exchanged using SystemVerilog class methods instead of signals. TLM-1 Method Types Overview UVM TLM-1 defines four major interface method types: Each method serves a specific communication purpose. In addition to blocking methods like put(), get(), and peek(), UVM TLM-1 also provides non-blocking variants. We will discuss about each methods in detail. put() Method: put() is used to send a transaction from a producer to a consumer. Blocking vs Non-Blocking ... Read more
- [Introduction to UVM TLM](https://vlsiworlds.com/uvm/introduction-to-uvm-tlm/): Transaction Level Modeling (TLM) is a communication mechanism where data is transferred as transactions (objects) instead of individual signals. In UVM, a transaction is usually a sequence item that contains multiple fields such as address, data, control bits, etc. Without TLM (Signal Level) With TLM (Transaction Level) Why Do We Need TLM? TLM helps to: All modern UVM environments use TLM-based communication. Basic TLM Building Blocks in UVM TLM communication uses five basic elements: What is TLM-1 in UVM? TLM-1 provides simple, method-based communication between components using function and task calls. It supports: Common TLM-1 Interfaces We will discuss more about ... Read more
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- [difference between $display, $write, $strobe and $monitor](https://vlsiworlds.com/miscellaneous/difference-between-display-write-strobe-and-monitor/): In SystemVerilog and Verilog, simulation system tasks are widely used to print signal values, debug designs, and observe behaviour during simulation. Among these, $display, $write, $strobe, and $monitor are the most commonly used output system tasks. Although they look similar, they behave very differently with respect to timing, formatting, and execution. Understanding these differences is extremely important for debugging RTL, writing testbenches, and preparing for VLSI interviews. 1. $display $display prints the specified message immediately when the statement is executed and automatically moves to the next line after printing. Key Characteristics Syntax 2. $write $write is similar to $display, but does ... Read more
- [VLSI AI Assistant - Built for Real Chip Engineers](https://vlsiworlds.com/vlsi-ai-assistant/): An AI assistant trained for RTL, UVM, Assertions, CDC, Low Power and Industry Protocols — powered by curated semiconductor knowledge and VLSIWorlds content. Click on the button to access: Advanced AI Features 🧠 Chain-of-Thought ReasoningThe assistant breaks down complex problems step-by-step to provide deeper and more logical explanations. 📚 Smart Chunking StrategyYour questions are matched against carefully structured knowledge chunks from VLSI resources, ensuring accurate and context-aware responses. 🎯 Domain-Specific KnowledgeFocused on SystemVerilog, UVM, verification concepts, and semiconductor fundamentals. 🔐 Login Benefits Guest users can explore. Logged-in users get: Your previous technical discussions stay saved. What Makes This Different? Most AI ... Read more
- [FIFO in VLSI](https://vlsiworlds.com/miscellaneous/fifo-in-vlsi/): FIFO(First-In-First-Out) is a basic memory structure that finds widespread application in VLSI design to perform data buffering and communication between system blocks. FIFO permits data to be read and written in the same order in which it was inputted, which makes it well-suited to those applications where preserving the order of data is of paramount importance. There are two primary types of FIFOs in VLSI design: synchronous FIFO and asynchronous FIFO. Synchronous FIFO A synchronous FIFO has one clock domain in which read and write operations are both driven by the same clock. This keeps the design simple since there is ... Read more
- [UVM Callback in UVM Sequence](https://vlsiworlds.com/uvm/uvm-callback-in-uvm-sequence/): UVM callback in UVM Sequence is similar to using callback in UVM driver. Before going through this article, I will suggest you to refer UVM Callbacks. In a verification environment, sequences generate stimulus for the DUT (Device Under Test). Sometimes, test scenarios require modifications to a base sequence without modifying it directly. Callbacks enable this by injecting custom behaviors, such as error injection, monitoring, or modifying transactions dynamically. UVM callbacks in sequences offer a powerful way to modify sequence behavior dynamically without altering the core sequence implementation. They enable greater flexibility and reusability in testbenches, making it easier to handle variations ... Read more
- [UVM Callbacks](https://vlsiworlds.com/uvm/uvm-callbacks/): Universal Verification Methodology (UVM) provides a robust mechanism for verification engineers to develop reusable and scalable testbenches. One powerful feature of UVM is the callback mechanism, which allows dynamic modification of testbench behavior without altering the original codebase. Please refer systemverilog callback to have a better understanding. UVM callbacks are a way to insert custom behavior into pre-existing components dynamically. They enable greater flexibility by allowing testbench modifications without directly changing the UVM component code. For example, in a UVM driver, callbacks can be used to alter transaction handling, inject errors, or monitor signals dynamically. UVM Callback Macros: UVM provides macros ... Read more
- [RAL Model Example](https://vlsiworlds.com/uvm/ral-model-example/): This UVM testbench demonstrates register read/write operations using UVM Register Abstraction Layer (RAL) without an actual DUT. Explanation of Components: This UVM RAL implementation enables register modeling and interaction using the APB protocol. Output: Next Step: Integrate with a DUT → If a DUT is added, the driver will communicate with actual hardware, and real register values will be returned instead of 0xDEADBEEF.
- [UVM RAL: Register Defines, Model Types, Enums, and Model Defines](https://vlsiworlds.com/uvm/uvm-ral-register-defines-model-types-enums-and-model-defines/): The UVM Register Abstraction Layer (RAL) provides a structured approach to defining and verifying memory-mapped registers in a UVM testbench. It abstracts the register interface, making it easier to perform read/write operations, predictions, and functional coverage. This article will cover: Additionally, we will explain important UVM RAL enumerations such as uvm_status_e, uvm_path_e, uvm_check_e, uvm_access_e, uvm_predict_e, and uvm_reg_mem_tests_e. 1. UVM RAL Register Defines UVM RAL provides various macros and base classes to simplify the register model implementation. Common UVM RAL Register Defines: Example: Defining a Register in UVM RAL 2. UVM RAL Model Types UVM RAL provides several data types to manage ... Read more
- [Coverage Practice Questions](https://vlsiworlds.com/system-verilog/coverage-practice-questions/): 2. Write SV code using coverage for 4-bit variable such that all bits toggle at least once. 3. Write a SV code using cross coverage for 4 bit variable x  and 2 bit variable a excluding below possibilities. X=5 && a=0,1 X=7 && a=2,3
- [UVM RAL Predictor](https://vlsiworlds.com/uvm/uvm-ral-predictor/): A UVM RAL Predictor is responsible for updating the UVM register model with the expected values based on bus transactions. When a register write occurs, the predictor updates the register model to reflect the new value. When a read occurs, the predictor compares the expected value with the actual value read from the DUT. Why is UVM RAL Predictor Important? There are two types of prediction methods in UVM: 1. Implicit Prediction In implicit prediction, the UVM register model automatically updates itself without needing a predictor component. When a register write transaction occurs, the register model assumes that the written value ... Read more
- [UVM RAL Adapter](https://vlsiworlds.com/uvm/uvm-ral-adapter/): A UVM RAL adapter is a class that converts register transactions from the UVM register model into corresponding bus transactions that can be understood by the DUT. The adapter ensures that the read/write operations performed on the register model are translated into appropriate sequences on the DUT’s bus interface (such as AXI, APB, AHB, or custom protocols). In other words, the UVM RAL Adapter acts as a bridge between the UVM register model and the actual bus interface used to communicate with the DUT (Device Under Test). Key Responsibilities of UVM RAL Adapter: To implement a UVM RAL adapter, we extend ... Read more
- [Registers Access Methods in UVM RAL](https://vlsiworlds.com/uvm/registers-access-methods-in-uvm-ral/): The Universal Verification Methodology (UVM) Register Abstraction Layer (RAL) provides a structured way to interact with hardware registers during functional verification. UVM RAL simplifies the process of accessing registers, verifying values, and predicting system behavior. In this article, we’ll explore various register access methods, including: We’ll also discuss front-door vs. back-door access and when to use each method. 1. Read and Write Methods The read() and write() methods are the most common ways to access registers in UVM. Syntax: Parameters Example: Front-Door vs. Back-Door Access 2. Peak and Poke Methods These are alternative ways to access register values. Peak (Read Without ... Read more
- [UVM RAL Classes Methods](https://vlsiworlds.com/uvm/uvm-ral-classes-methods/): The UVM Register Abstraction Layer (RAL) is a powerful feature of the Universal Verification Methodology (UVM) that helps manage memory-mapped registers in a testbench. It simplifies register modeling, read/write operations, and checking expected values against actual hardware responses. This article explores various UVM RAL classes and their methods, including: We’ll cover their methods, functionality, and examples to help you to integrate them into your UVM environment. 1. uvm_reg_block – Register Block A register block represents a group of registers or memory within a design. It helps organize registers into hierarchical structures. Common Methods in uvm_reg_block Method Description create_map() Creates a register ... Read more
- [AXI Wrap Address Calculation](https://vlsiworlds.com/miscellaneous/axi-wrap-address-calculation/): AXI (Advanced eXtensible Interface) is a widely used protocol in modern SoC (System on Chip) designs, primarily due to its efficiency in handling high-speed data transfers. One key feature of AXI is its burst transactions, which allow multiple data transfers to occur with a single address phase. Among different burst types, the wrap burst is particularly useful for cache operations. A wrap burst is a special type of burst mode in AXI where the address wraps around within a fixed boundary. This ensures that memory accesses remain within a predefined address range, making it particularly useful for cache-line fills and circular ... Read more
- [UVM RAL Model](https://vlsiworlds.com/uvm/uvm-ral-model/): A UVM RAL model consists of multiple hierarchical blocks that represent the design’s register architecture. The key components of a UVM RAL model include: 1. uvm_reg (Register) The uvm_reg class represents a single hardware register. It encapsulates details like: Registers provide built-in operations such as write(), read(), and mirror() to interact with the DUT. 2. uvm_reg_field (Register Field) Each register contains one or more fields, represented by the uvm_reg_field class. A register field defines: Register fields allow fine-grained access to specific bits within a register. 3. uvm_mem (Memory) The uvm_mem class represents memory elements in the design. It models blocks of ... Read more
- [UVM RAL Introduction](https://vlsiworlds.com/uvm/uvm-ral-introduction/): The UVM Register Abstraction Layer (RAL) is a critical component of the Universal Verification Methodology (UVM) that simplifies the verification of register-based designs. It provides a structured way to define, access, and manipulate registers and memories in a testbench, ensuring a consistent and reusable approach for verification. The UVM Register Abstraction Layer (RAL) automates register verification by: With UVM RAL, verification engineers can interact with registers at a higher level without worrying about low-level details like bus protocols and direct transactions. UVM RAL is not mandatory to use, but it does the job efficiently. Using UVM RAL offers several advantages: RAL ... Read more
- [Cache Memory Working Mechanism](https://vlsiworlds.com/miscellaneous/cache-memory-working-mechanism/): Cache memory is built using Static RAM (SRAM) rather than Dynamic RAM (DRAM), which is used for main memory (RAM). The reason behind this choice is that SRAM is much faster than DRAM, though it is also more expensive and consumes more power. Key Features of Cache Memory Construction: Components of Cache Memory Cache memory consists of several essential components that enable efficient data retrieval and management: 1. Cache Controller 2. Cache Memory Blocks (Cache Lines) 3. Tags 4. Data Store 5. Address Mapping Mechanism 6. Replacement Policy Unit 7. Write Policy Unit How Cache Memory Works? Cache memory operates using ... Read more
- [RAL Tutorial](https://vlsiworlds.com/uvm/ral-tutorial/)
- [UVM Testbench and Class Hierarchy](https://vlsiworlds.com/uvm/uvm-introduction-and-class-hierarchy/): Universal Verification Methodology (UVM) is a standardized verification methodology used in the semiconductor industry to create reusable, scalable, and efficient testbenches for verifying digital designs. Developed by Accellera, UVM is based on SystemVerilog and provides a powerful framework for building complex verification environments. It helps engineers manage testbenches in a structured way, ensuring better code reuse, automation, and improved debugging capabilities. Verification of modern digital designs is becoming increasingly complex, requiring structured methodologies to ensure thorough testing. UVM provides: UVM Class Hierarchy UVM is built on an object-oriented framework using SystemVerilog classes. The class hierarchy is the backbone of UVM, defining ... Read more
- [UVM Subscriber](https://vlsiworlds.com/uvm/uvm-subscriber/): A UVM subscriber is a specialized component derived from uvm_subscriber that is primarily used to receive and process transactions. It is often utilized in scoreboards, coverage collectors, or monitors to analyze simulation data. Mostly we use uvm_subscriber for functional coverage monitor. A subscriber typically: Unlike a monitor, which captures DUT activity and forwards data to multiple components, a subscriber’s primary role is to consume and process transactions. Structure of a UVM Subscriber A user-defined subscriber class is extended from uvm_subsriber. uvm_subscriber is inherited by uvm_component. A UVM subscriber typically consists of: Example: Implementing a UVM Subscriber Let’s walk through a simple ... Read more
- [UVM testbench top](https://vlsiworlds.com/uvm/uvm-testbench-top/): The testbench top is the highest-level component in a UVM testbench. It is responsible for instantiating and connecting all the major verification components, ensuring the DUT (Design Under Test) is properly stimulated and monitored. The testbench top typically resides in the testbench module and interacts with the simulation environment, providing an interface to the DUT and managing simulation execution. Key Components of the UVM Testbench Top The UVM testbench top usually contains the following key components: 1. DUT (Design Under Test) Instance The DUT is the hardware design that needs to be verified. It is instantiated in the testbench top and ... Read more
- [Cache Memory](https://vlsiworlds.com/miscellaneous/cache-memory/): Cache memory is a small, high-speed storage unit that temporarily holds frequently used data and instructions. It is significantly faster than RAM and is typically embedded within or located close to the CPU. The primary purpose of cache memory is to reduce the time required to access data from the main memory, thereby improving the overall performance of the system. Whenever the CPU needs data, it first checks the cache memory. If the required data is found there, it eliminates the need to fetch it from the slower RAM, leading to faster execution of processes. Types of Cache Memory Cache memory ... Read more
- [UVM Sequence Item](https://vlsiworlds.com/uvm/uvm-sequence-item/): A uvm_sequence_item is a SystemVerilog class that represents a transaction. It is used to communicate between the sequencer and the driver in a UVM testbench. It typically contains: To create a sequence item, we need to extend uvm_sequence_item and define the required fields. Key Points: Example: Creating a basic transaction class
- [UVM Sequence item Methods](https://vlsiworlds.com/uvm/uvm-sequence-item-methods-2/): One of the key components in UVM is the sequence item (uvm_sequence_item), which represents transactions in a testbench. UVM provides several built-in methods for sequence items to facilitate debugging, comparison, and data manipulation. In this article, we will explore the most commonly used UVM sequence item methods with examples: 1. create() Method The create() method is used to instantiate an object dynamically using the UVM factory. It ensures that objects are created correctly and allows for factory overrides. Example: Why use create()? 2. print() Method The print() method displays the contents of a sequence item, making it useful for debugging. Example: ... Read more
- [UVM Sequence item Methods](https://vlsiworlds.com/uvm/uvm-sequence-item-methods/): One of the key components in UVM is the sequence item (uvm_sequence_item), which represents transactions in a testbench. UVM provides several built-in methods for sequence items to facilitate debugging, comparison, and data manipulation. In this article, we will explore the most commonly used UVM sequence item methods with examples: 1. create() Method The create() method is used to instantiate an object dynamically using the UVM factory. It ensures that objects are created correctly and allows for factory overrides. Example: Why use create()? 2. print() Method The print() method displays the contents of a sequence item, making it useful for debugging. Example: ... Read more
- [UVM Object and Utility Macros](https://vlsiworlds.com/uvm/uvm-object-and-utility-macros/): The Universal Verification Methodology (UVM) provides a powerful and flexible framework for verifying digital designs. One of the key building blocks in UVM is the UVM object, which is used for data storage, stimulus generation, and communication between different verification components. In this article, we’ll explore UVM objects, the UVM utility macros, and the UVM field macros—which simplify object creation, debugging, and automation. We’ll also provide examples to illustrate their use. What is a UVM Object? A UVM object is a class that extends uvm_object and is primarily used for data storage and communication. Unlike uvm_component, which represents structural elements like ... Read more
- [UVM Test](https://vlsiworlds.com/uvm/uvm-test/): In UVM, UVM test component is a specialized object that sets up the verification environment and controls the execution of tests. It coordinates stimulus generation, DUT interactions, and result checking, ensuring that the design behaves as expected. Test components are typically derived from the uvm_test base class, providing a customizable way to implement test cases for different scenarios. Steps to Write a UVM Test Component To create an effective UVM test component, we should follow these steps: 1. Define the Test Component Class Start by creating a new class for your test. This class should extend the uvm_test base class. The ... Read more
- [UVM Sequence Macros](https://vlsiworlds.com/uvm/uvm-sequence-macros/): UVM (Universal Verification Methodology) provides several predefined macros to simplify the creation and management of sequences in a testbench. These macros significantly reduce boilerplate code, making sequences easier to write, debug, and maintain. 1. `uvm_object_utils The uvm_object_utils macro is used to register a sequence class with the UVM factory. This enables dynamic creation of sequences using the factory mechanism, which is essential for features like factory overrides and reusability. We need to place this macro in the sequence class definition. Code Example: Explanation: 2. `uvm_do The uvm_do macro simplifies the process of creating, randomizing, and sending a sequence item. It is ... Read more
- [Virtual Sequencers and Virtual Sequences in UVM](https://vlsiworlds.com/uvm/virtual-sequencers-and-virtual-sequences-in-uvm/): A virtual sequencer is a UVM component that does not directly control any drivers or interfaces. Instead, it coordinates the execution of multiple sequences running on different sequencers. Virtual sequencers are crucial in verifying systems with multiple agents, where the interactions between agents need to be synchronized and controlled. In other words, if there are multiple driving agents and simulation coordination is required between them, we will need a virtual sequencer. A virtual sequencer is not connected to a driver. Key Points: What is a Virtual Sequence in UVM? A virtual sequence is a specialized sequence that runs on a virtual ... Read more
- [DDR4 SDRAM Protocol](https://vlsiworlds.com/miscellaneous/ddr4-sdram-protocol/): DDR4 SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is a widely used memory standard in modern computing systems due to its high performance, low power consumption, and large storage capacity. It is essential in devices ranging from personal computers to servers, graphics cards, and embedded systems. This article delves into the structure of DDR4, how read and write operations work, the role of refreshing, precharge commands, timing parameters, and the function of sense amplifiers. Structure of DDR4 SDRAM The internal structure of DDR4 SDRAM is highly organized, designed to allow efficient access to large amounts of memory at high ... Read more
- [Miscellaneous](https://vlsiworlds.com/miscellaneous/)
- [Start a sequence in UVM](https://vlsiworlds.com/uvm/start-a-sequence-in-uvm/): In Universal Verification Methodology (UVM), sequences are used to generate transactions that drive stimulus to the DUT (Device Under Test). However, understanding how to start a sequence and manage its communication with the sequencer and driver is critical to implementing an efficient and reusable UVM testbench. The sequence, sequencer, and driver are the primary components involved in transaction generation and delivery. Sequences must be associated with a sequencer so they can send transactions. This is done when starting the sequence. The sequencer is most probably the m_sequencer which have reference to the sequencer on which sequence is running. Example: Here, env.agent.axi_seqr ... Read more
- [UVM Sequence](https://vlsiworlds.com/uvm/uvm-sequence/): The UVM sequence is a core component of the Universal Verification Methodology (UVM) and plays a crucial role in generating and delivering stimulus to the DUT (Device Under Test). As a user-defined class extending the uvm_sequence base class, the UVM sequence defines the behavior of transactions and interacts with the sequencer to generate stimuli in a controlled and organized manner. A UVM sequence is a transaction generator. It defines the flow of transactions that are sent to the driver via the sequencer. Sequences can call other sequences, enabling hierarchical and modular test creation. A user-defined sequence class is extended from uvm_sequence. ... Read more
- [UVM Driver](https://vlsiworlds.com/uvm/uvm-driver/): The UVM driver is a critical component in the Universal Verification Methodology (UVM) testbench architecture. It acts as a bridge between the sequencer and the DUT (Device Under Test). By converting transaction-level stimulus generated by the sequencer into pin-level signals, the driver ensures accurate communication between the testbench and the DUT. The UVM driver extends from the uvm_driver base class and is inherited by uvm_component. It should be parameterized with request(REQ) and response(RSP) sequence_item types. Response is optional. uvm_driver is responsible for: In short, the driver works at the signal level, translating abstract data structures (transactions) into protocol-specific signals on the ... Read more
- [m_sequencer and p_sequencer in UVM](https://vlsiworlds.com/uvm/m_sequencer-and-p_sequencer-in-uvm/): m_sequencer: The m_sequencer is a handle to the sequencer instance in the sequence. It is default sequencer. It provides access to the sequencer’s methods and properties. The m_sequencer is automatically created and managed by UVM. It is used internally by the sequence to communicate with the sequencer. Users typically do not interact with m_sequencer directly. p_sequencer: The p_sequencer is a type-specific reference to the parent sequencer. It allows sequences to interact with user-defined methods or attributes in a customized sequencer. When you extend the UVM sequencer and define additional functionality, sequences can access this functionality via p_sequencer. It requires type casting ... Read more
- [UVM Sequencer](https://vlsiworlds.com/uvm/uvm-sequencer/): In Universal Verification Methodology (UVM), the sequencer is a critical component responsible for managing and controlling the flow of transactions to the driver, ensuring a well-structured and flexible testbench architecture. It coordinates the generation of stimulus by interacting with sequences and passing transactions to the driver. It acts as a mediator between the sequence, which generates transaction-level stimulus, and the driver, which converts these transactions into pin-level signals for the design under test (DUT). A user-defined sequencer class is extended from uvm_sequencer. It should be parameterized with request(REQ) and response(RSP) item types. Response is optional. uvm_sequencer is inherited by uvm_component. The ... Read more
- [UVM Scoreboard](https://vlsiworlds.com/uvm/uvm-scoreboard/): The Universal Verification Methodology (UVM) scoreboard is a crucial component in functional verification, enabling the verification of the design under test (DUT) by comparing expected and actual outputs. The expected outputs can come from a reference model or they can be golden reference values. A well-designed scoreboard ensures that the DUT behaves as intended under various test scenarios. A user-defined scoreboard class is extended from uvm_scoreboard. uvm_scoreboard is inherited by uvm_component. Components of a UVM Scoreboard The communication between monitor and scoreboard will happen through TLM ports and exports. Steps to Create a UVM Scoreboard Example: Writing a UVM Scoreboard Design ... Read more
- [UVM Environment](https://vlsiworlds.com/uvm/uvm-environment/): The UVM environment acts as the container for the UVM components including one or more agents, monitors, scoreboards and checkers. The communication between Monitor and other components like scoreboard or subscriber happens here. A user-defined environment class is extended from uvm_env. uvm_env is inherited by uvm_component. Example: Implementing a UVM Env Let’s implement a simple UVM environment.
- [UVM Agent](https://vlsiworlds.com/uvm/uvm-agent/): In Universal Verification Methodology (UVM), the agent is a key component designed to encapsulate all the elements required to drive and monitor a DUT interface. It streamlines the verification process by integrating drivers, monitors, and sequencers into a single cohesive entity. A user-defined agent class is extended from uvm_agent. uvm_agent is inherited by uvm_component. A UVM agent is a reusable verification component that represents an interface of the Design Under Test (DUT). It consolidates three main elements: An agent can be of two types: Active vs. Passive Agents Active Agent: Contains all the three components a sequencer, a monitor and a ... Read more
- [UVM Monitor](https://vlsiworlds.com/uvm/uvm-monitor/): A UVM monitor is a passive component designed to observe and extract data from the DUT without influencing its behavior. It operates independently and does not drive any signals to the DUT. Instead, it listens to interface signals, converts them into transaction level signals and sends them to analysis components or other parts of the testbench like scoreboard or subscriber. A user-defined monitor class is extended from uvm_monitor. uvm_monitor is inherited by uvm_component. Key Responsibilities of a UVM Monitor Structure of a UVM Monitor A UVM monitor generally includes: Example: Implementing a UVM Monitor Let’s implement a simple UVM monitor.
- [uvm_config_db in UVM](https://vlsiworlds.com/uvm/uvm_config_db-in-uvm/): In UVM-based verification, components like agents, drivers, and monitors are often instantiated hierarchically. Sharing configuration information, such as register settings, queues, list, time delays, protocol-specific parameters or class handles between these components is a common requirement. The uvm_config_db is a centralized database used to store and retrieve this information. It enables decoupling between components, allowing parameters to be set at a higher level (e.g., the test) and retrieved by lower-level components without direct connections. This database is globally accessible. uvm_config_db is internally built on top of the uvm_resource_db, but it is not a direct extension (inheritance). Instead, it is a utility ... Read more
- [Verification and Testbench Components](https://vlsiworlds.com/system-verilog/verification-and-testbench-components/): The verification process using System Verilog ensures that a design behaves as intended by simulating it in a controlled test environment. A well-structured testbench plays a crucial role in this process. Let’s delve into the System Verilog verification process and its key testbench components. The Verification Process The verification process in SystemVerilog revolves around creating a reusable and scalable environment to test the design under verification (DUV). It typically involves the following steps: The Universal Verification Methodology (UVM), based on System Verilog, is often used to structure the testbench and process. Key Testbench Components in SystemVerilog A typical System Verilog testbench ... Read more
- [More Semaphore Examples](https://vlsiworlds.com/system-verilog/more-semaphore-examples/): Here, we will take few more examples to understand Semaphore thoroughly. Example 1: Assume that we have 3 processes, second process starts only after completing the first and 3rd starts only after completing the 2nd process. Let’s see how we can implement the situation using semaphore. Explanation
- [case statement](https://vlsiworlds.com/system-verilog/case-statement/): A case statement in SystemVerilog is a multi-way branch statement used to select one out of several blocks of code based on the value of an expression. It is analogous to the switch-case construct in programming languages like C or Java. Case statements provide a clean, readable way to represent multiple conditional operations. Syntax of a Case Statement The basic syntax of a case statement in System Verilog is as follows: Types of Case Statements in SystemVerilog Example: Case Statement in System Verilog Let’s consider a simple 4-bit ALU (Arithmetic Logic Unit) operation selector. Depending on the operation code (opcode), the ... Read more
- [while and do while loop](https://vlsiworlds.com/system-verilog/while-and-do-while-loop/): SystemVerilog provides two types of conditional looping constructs: while and do-while loops. These loops are used to repeatedly execute a block of code as long as a specified condition remains true. While similar in purpose, they differ in how they evaluate the loop condition. The while Loop The while loop is a pre-condition loop, meaning it evaluates the condition before executing the loop body. If the condition is false at the start, the loop body will not execute at all otherwise it will keep executing the statements until the condition is true. Syntax Example 1: Basic Usage of while Output: Example ... Read more
- [Repeat and Forever Loop](https://vlsiworlds.com/system-verilog/repeat-and-forever-loop/): SystemVerilog provides a variety of looping constructs to handle repetitive operations, including the repeat and forever loops. While these loops are primarily used in simulation and testbench design, they can also simplify hardware modeling. Additionally, the forever loop and the always block are often compared due to their infinite execution, but they serve distinct purposes. The repeat Loop The repeat loop executes a block of code a fixed number of times. It is particularly useful when the number of iterations is predetermined. Syntax n: Specifies the number of iterations. The loop terminates automatically after n iterations. Example 1: Basic Usage of ... Read more
- [Foreach Loop](https://vlsiworlds.com/system-verilog/foreach-loop/): System Verilog provides the foreach loop as a convenient way to iterate through arrays and multi-dimensional arrays. Unlike traditional loops like for, which require explicit index management, the foreach loop simplifies the process by automatically iterating over each element of an array. This feature is especially useful in verification environments and hardware modeling where array operations like dynamic, associative, and multi-dimensional arrays are common. Syntax: Example 1: Iterating Over a One-Dimensional Array Example 2: Iterating Over a Multi-Dimensional Array Explanation: Example 3: Iterating Over Associative Arrays Explanation: Features of the foreach Loop
- [For loop in SV](https://vlsiworlds.com/system-verilog/for-loop-in-sv/): The for loop in SystemVerilog is a powerful construct that allows repeated execution of a block of code for a specified number of iterations. It is widely used in hardware modeling and verification for tasks like initializing arrays, generating repetitive structures, and performing iterative calculations. Basics of the for Loop The for loop is used when the number of iterations is known or can be determined programmatically. It consists of three parts: Syntax Example 1: Initializing an Array Explanation: Output: Example 2: Nested for Loops for Multi-Dimensional Arrays Nested for loops are used to iterate through multi-dimensional arrays. Explanation: Output: In ... Read more
- [If-else statement in SV](https://vlsiworlds.com/system-verilog/if-else-statement-in-sv/): The if-else statement is a fundamental conditional construct in SystemVerilog, widely used in hardware description and verification. It allows designers to implement decision-making logic based on specific conditions. In addition to if-else, SystemVerilog introduces features like else if for cascading conditions and unique if for improved simulation and synthesis efficiency. This article explains these constructs with examples to help you effectively use them in your designs. Basics of if-else The if-else statement evaluates a condition and executes corresponding code blocks based on whether the condition is true or false. The begin and end are required if we are using multiple statements ... Read more
- [Assertion Practice Questions](https://vlsiworlds.com/system-verilog/assertion-practice-questions/): 2. If signal “a” is high on a given positive clock edge, then signal “b” will be high eventually starting from the next clock cycle. 3.  If the signal “a” is high on given posedge of clock, then signal “b” should be high for 3 clock cycles followed by “c” should be high after ”b” is high for third time. 4. Write an assertion checker to make sure that an output signal never goes X. 5. When signal_a is asserted, signal_b must be asserted, and must remain up until one of the signals signal_c or signal_d is asserted. 6. write a ... Read more
- [Constraint Practice Questions](https://vlsiworlds.com/system-verilog/constraint-practice-questions/): 2. Write SV code using constraint on array size < 10 and array contents sum =100. 3.  Write a SV code using constraint to generate 10 ones without using $countones for a variable. 4. write SV code using constraint for generating multiples of 16 . 5. write the constraint for an 10bit variable and display the values in descending order and explain with example values. 6. Write a constraint for storing the even numbers in odd locations and odd numbers in even locations by using dynamic array. 7. Write a SV code using constraint for 16bit addr to generate power of ... Read more
- [Binding with assertions](https://vlsiworlds.com/system-verilog/binding-with-assertions/): Binding is the process of associating assertions, written in SystemVerilog Assertion (SVA) constructs, with a design module or interface without directly modifying the source code of the DUT. This approach is particularly beneficial in: Why Use Binding? Binding assertions provides several advantages: Syntax Example: We design a simple 4-bit counter that increments on every positive clock edge when enable is high. The counter resets to 0 when rst_n is low. In assertion module we define a property no_overflow that ensures the counter doesn’t overflow when enable is high. An assert statement checks the property and reports an error if violated. TB ... Read more
- [Repetition Operators](https://vlsiworlds.com/system-verilog/repetition-operators/): Before going to repetition operators, first understand about the types of clock delays we use while writing our various assertions. Simple Operator Clock Delays: 1. ##  : represents cycle delay (or rather no of sampling edges) 2. ##n – specifies “n” clock cycles 3. ##0 – represents same clock cycle – overlapping signals 4. ## [min:max] – Specifies a range of clock cycles, where min and mux must be 0 or greater. $ specifies infinite number of cycles. This sequence tells that once valid is high, ready must be asserted 1 clock cycle later. Here once the req signal is true, the grant ... Read more
- [typedef class in System Verilog](https://vlsiworlds.com/system-verilog/typedef-class-in-system-verilog/): The typedef construct allows you to create type aliases for various data types, including classes. Using typedef with classes simplifies code management, improves readability, and promotes modular design. In System Verilog, there are scenarios where a class handle of another class is required before the actual class definition is available. To handle such cases, System Verilog provides forward declaration of classes using the typedef keyword. This feature allows you to declare a class type without defining its contents, enabling the use of the class handle in declarations, parameters, or method arguments before its full definition is known. What is Forward Declaration? ... Read more
- [Disable iff and ended construct in assertions](https://vlsiworlds.com/system-verilog/disable-iff-and-ended-construct-in-assertions/): disable iff in Assertions The disable iff construct in SystemVerilog is used to conditionally disable an assertion. When the condition specified in disable iff evaluates to true, the assertion is disabled, and no failure will be reported, regardless of the assertion’s outcome. Syntax How It Works When the condition in disable iff is true, the assertion is temporarily ignored. Example: Assertion with disable iff Scenario You want to monitor that the data_ready signal is asserted within 5 clock cycles after req is asserted. However, the assertion should be ignored if the reset signal is active. Explanation ended Construct in Sequences The ... Read more
- [Extern method in classes](https://vlsiworlds.com/system-verilog/extern-method-in-classes/): One powerful feature of System Verilog OOP approach is the use of extern methods in classes. The extern keyword allows you to define class methods outside the class body, improving code modularity and readability. In System Verilog, extern methods are function or task declarations in a class whose definitions are provided outside the class body. This separation of declaration and definition enhances the organization of code, especially in large projects. Syntax of extern Methods General Syntax: Key Points to Remember Example 1: A Simple Counter Class Output: Explanation of the Example
- [Built-in methods in assertions](https://vlsiworlds.com/system-verilog/built-in-methods-in-assertions/): Built-in methods in assertions are designed to simplify complex logic and make verification more efficient and comprehensible. These methods are implemented in hardware description languages (HDLs) and assertion libraries like SystemVerilog Assertions (SVA) to analyze and validate temporal properties of a design. Let’s delve into some commonly used built-in methods such as $rose, $fell, $stable, $past, $onehot, $onehot0, $countones, $isunknown, and others. We’ll explore their purposes, use cases, and examples. 1. $rose The $rose function checks if least significant bit (LSB) of a signal or expression transitions from 0 or x or z (previous clocking value) to 1 in a given ... Read more
- [Until and within operator](https://vlsiworlds.com/system-verilog/until-and-within-operator/): The Within Operator The within operator ensures that a specific event or condition occurs within the time range defined by another event or condition. Syntax Example: Data Transfer Completion In a data transfer system, the transfer_complete signal must occur during the active period of the transfer_enable signal. Explanation The Until Operator The until operator checks that a condition remains true until another event occurs. Once the terminating event occurs, the first condition is no longer monitored. Syntax Example: Reset Stability Until Load The reset signal must remain active until the load operation begins. Explanation Example: Let’s take one more example. In ... Read more
- [Program Block in System Verilog](https://vlsiworlds.com/system-verilog/program-block-in-system-verilog/): SystemVerilog introduced the program block to address the needs of testbench development. It provides a dedicated context for writing verification code that interacts with the design under test (DUT). While similar in structure to the traditional module, the program block serves a specific purpose and has distinct characteristics. This article explores the program block, its features, and how it differs from the module block, with examples to illustrate its usage. What is a Program Block? A program block in SystemVerilog is a construct designed specifically for testbenches. It encapsulates verification logic, ensuring a clear separation between testbench code and the DUT. ... Read more
- [throughout and not operator](https://vlsiworlds.com/system-verilog/throughout-and-not-operator/): Throughout Operator The throughout operator in SystemVerilog is used to assert that one condition (antecedent) must remain true for the entire duration when another condition (consequent) is true. It ensures that the first condition does not break or change state while the second condition holds. Example: The property checks that whenever data_ready is high, the data_valid signal stays high for the entire duration. The data_ready signal indicates readiness to accept data. The assertion ensures that data_valid remains high throughout the duration of data_ready. Key Characteristics of the Throughout Operator Not Operator The not operator negates a condition, ensuring it does not ... Read more
- [Casting in System Verilog](https://vlsiworlds.com/system-verilog/casting-in-system-verilog/): System Verilog offers advanced type conversion techniques to handle data of different types. Casting is an essential feature that allows developers to convert a variable from one data type to another. In System Verilog, casting is broadly categorized into static casting and dynamic casting. This article explains both with detailed examples. Static Casting in SystemVerilog Static casting is a compile-time operation where the programmer explicitly converts one data type to another. It is primarily used to ensure compatibility between different types and sizes, allowing developers to manage type mismatches. Syntax Example: Static Casting Output: Key Characteristics Dynamic Casting in SystemVerilog Dynamic ... Read more
- [System Verilog break and continue](https://vlsiworlds.com/system-verilog/system-verilog-break-and-continue/): System Verilog, a widely used hardware description and verification language, provides control flow constructs to make loops more flexible and powerful. Among these constructs, the break and continue statements play a pivotal role in managing loop execution. This article delves into these statements, explaining their purpose, usage, and practical examples. Break Statement The break statement is used to terminate the execution of a loop prematurely. When encountered, it causes the program to exit the current loop immediately, regardless of the loop’s conditional expression. This is particularly useful when a certain condition is met, and continuing the loop serves no further purpose. ... Read more
- [Implication Operator in Assertions](https://vlsiworlds.com/system-verilog/implication-operator-in-assertions/): In SystemVerilog Assertions (SVA), the implication operator is a powerful construct used to establish a cause-and-effect relationship between conditions. It ensures that when a certain condition (antecedent) holds true, another condition (consequent) must follow, either immediately or after a delay. This article delves into the two types of implications—overlapped and non-overlapped—with detailed explanations and examples. Implication in Assertions The implication operator in SystemVerilog comes in two forms: Syntax Overlapped Implication (|->) The overlapped implication asserts that whenever the antecedent condition is true, the consequent condition must hold starting in the same clock cycle. Example: Simple Overlapped Implication In this example: If ... Read more
- [Sequence and Property in Assertions](https://vlsiworlds.com/system-verilog/sequence-and-property-in-assertions/): What is a Sequence in Assertions? A sequence defines an ordered set of events or conditions over time. Sequences capture temporal relationships between signals, such as when specific conditions must hold over a series of clock cycles. They are the building blocks for properties, making them essential for writing expressive assertions. Syntax Example: A Simple Sequence Suppose we want to define a sequence where a signal req is followed by a signal ack within two clock cycles. Here: What is a Property in Assertions? A property describes a condition that must hold for a given sequence. Properties are used to express ... Read more
- [Introduction to Assertions](https://vlsiworlds.com/system-verilog/introduction-to-assertions/): Assertions in SystemVerilog are a powerful feature used for design verification and debugging. They help ensure that certain properties or behaviors in a design are always met, both during simulation and in real-world usage. Assertions provide a concise, readable way to express conditions that must hold true. In this article, we’ll explore immediate and concurrent assertions, their differences, and examples to illustrate their usage. What Are Assertions? In the context of SystemVerilog, an assertion is a statement that checks a specific condition or set of conditions. If the condition fails during simulation, the assertion can generate a warning or error, allowing ... Read more

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