throughout and not operator

Throughout Operator

The throughout operator in SystemVerilog is used to assert that one condition (antecedent) must remain true for the entire duration when another condition (consequent) is true. It ensures that the first condition does not break or change state while the second condition holds.

Example:

property data_valid_check;
    @(posedge clk) data_valid throughout data_ready;
endproperty

assert property (data_valid_check)
    else $error("Data is invalid while ready signal is high.");

The property checks that whenever data_ready is high, the data_valid signal stays high for the entire duration. The data_ready signal indicates readiness to accept data. The assertion ensures that data_valid remains high throughout the duration of data_ready.

Key Characteristics of the Throughout Operator

  1. Continuous Monitoring: It ensures that the antecedent remains true throughout the duration of the consequent.
  2. Temporal Scope: The operator checks conditions over time, not just at a single simulation cycle.
  3. Assertion Context: Typically used in property definitions and verification environments to validate sustained behavior.

Not Operator

The not operator negates a condition, ensuring it does not occur during a specified time or under a given scenario.

Syntax

not (condition)
  • condition: The condition or event that must not occur.

Example: Avoid Spurious Transactions

The system must ensure that no transaction occurs while the system is in reset.

property no_transaction_during_reset;
    @(posedge clk) not (transaction) |-> reset;
endproperty

assert property (no_transaction_during_reset)
    else $error("Transaction occurred during reset.");

Explanation

  • The assertion checks that the transaction signal does not go high while reset is active.
  • If transaction is asserted during reset, the assertion fails.
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