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- What are virtual sequences and virtual sequencers?
- What is difference between create and new() function?
- Explain the handshake mechanism between driver and sequencer?
- What are UVM phases? Why build phase is top-down?
- What is config_db? Write down the syntax and explain it’s context?
- What is difference between uvm_config_db and uvm_resource_db?
- What is TLM_PORT and UVM Analysis port? Tell the difference between them.
- What is factory overriding?
- What are UVM Macros?
- What is difference between uvm_component and uvm_object?
- What is active agent and passive agent?
- How the transaction happens between sequence, sequencer and driver?
- How monitor is connected to scoreboard?
- What is phase_raise_objection and drop_objection? Why do we use?
- What is adaptor and predictor in UVM RAL?
- Why do we use phase_raise_objection and phase_drop_objection in UVM?
