Which is easier to grab a job for a Fresher in DV role or RTL Design role? Which role has the maximum opening?
I am an 3rd year ECE student from tier 3 college, know Verilog and VHDL, done Internship on FPGA implemntation of Digital FM modulator and Demodulator(All-Digital Phase Locked loop based) from NIT Jamshedpur.
As no company visit for campasing so I have to try for offcampus. But I am confused for which role should I prepare DV or RTL Design keeping in mind future opportunies as a need a job as soon as a left college.
Hi, You are a 3rd year ECE student from tier 3 college and you already know verilog and VHDL. Since you want a job just after completing your college, I will recommend you to go after DV. DV should be your primary target and RTL Design, you can keep as a secondary target. Me and my friends are seeing lot of DV openings compare to other fields. RTL Design jobs are also there but they are mostly for senior levels. Also for DV role, your internship on FPGA implementation of Digital FM modulator and Demodulator(All-Digital Phase Locked loop based) won’t matter since it’s not related to DV. I will suggest you to learn System Verilog and basics of UVM as well. Now a days, competition in DV is high and it won’t be easy to make an entry in DV as a fresher. Do some projects like FIFO implementation and verification, RISC processor etc. Having a knowledge of basic protocols like APB, AXI will be a plus point. Ask referrals from your seniors or friends which are already in this industry. Just prepare well and you will do fine.